diff options
| author | Martin Fuzzey <mfuzzey@parkeon.com> | 2016-01-14 07:36:26 +0300 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2016-01-25 21:37:44 +0300 |
| commit | 8d1a0ae724ad74ef7946a45e3b2d3e01f39df02b (patch) | |
| tree | 95c4e633c5ef8ae16bd3233ecee9f5e1e2b66623 /Documentation/devicetree/bindings/arm/pmu.txt | |
| parent | 92e963f50fc74041b5e9e744c330dca48e04f08d (diff) | |
| download | linux-8d1a0ae724ad74ef7946a45e3b2d3e01f39df02b.tar.xz | |
ARM: perf: Set ARMv7 SDER SUNIDEN bit
ARMv7 counters other than the CPU cycle counter only work if the Secure
Debug Enable Register (SDER) SUNIDEN bit is set.
Since access to the SDER is only possible in secure state, it will
only be done if the device tree property "secure-reg-access" is set.
Without this:
Performance counter stats for 'sleep 1':
14606094 cycles # 0.000 GHz
0 instructions # 0.00 insns per cycle
After applying:
Performance counter stats for 'sleep 1':
5843809 cycles
2566484 instructions # 0.44 insns per cycle
1.020144000 seconds time elapsed
Some platforms (eg i.MX53) may also need additional platform specific
setup.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com>
Signed-off-by: George G. Davis <george_davis@mentor.com>
[will: add warning if property is found on arm64]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/pmu.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/pmu.txt | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt index 56518839f52a..b6056d3bca06 100644 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ b/Documentation/devicetree/bindings/arm/pmu.txt @@ -46,6 +46,16 @@ Optional properties: - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd events. +- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register + (SDER) is accessible. This will cause the driver to do + any setup required that is only possible in ARMv7 secure + state. If not present the ARMv7 SDER will not be touched, + which means the PMU may fail to operate unless external + code (bootloader or security monitor) has performed the + appropriate initialisation. Note that this property is + not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux + in Non-secure state. + Example: pmu { |