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| author | Will Deacon <will@kernel.org> | 2022-03-14 22:00:44 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-03-14 22:00:44 +0300 |
| commit | cd92fdfcfa390ee5dac16f4b533b0c0adc6aff03 (patch) | |
| tree | bcc3dcdeeb682aff9c2a75ee61c92f985e4c1c9f /Documentation/arm64/silicon-errata.rst | |
| parent | b523d6b80fbcf45f64f5010424a273c32df79e7a (diff) | |
| parent | f90205b95368ee2b56fc523abda6c4d514901d9b (diff) | |
| download | linux-cd92fdfcfa390ee5dac16f4b533b0c0adc6aff03.tar.xz | |
Merge branch 'for-next/errata' into for-next/core
* for-next/errata:
arm64: Add cavium_erratum_23154_cpus missing sentinel
irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
Diffstat (limited to 'Documentation/arm64/silicon-errata.rst')
| -rw-r--r-- | Documentation/arm64/silicon-errata.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index ea281dd75517..466cb9e89047 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -136,7 +136,7 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | +----------------+-----------------+-----------------+-----------------------------+ -| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | +| Cavium | ThunderX GICv3 | #23154,38545 | CAVIUM_ERRATUM_23154 | +----------------+-----------------+-----------------+-----------------------------+ | Cavium | ThunderX GICv3 | #38539 | N/A | +----------------+-----------------+-----------------+-----------------------------+ |