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authorClément Léger <cleger@rivosinc.com>2024-06-19 14:35:13 +0300
committerPalmer Dabbelt <palmer@rivosinc.com>2024-06-26 17:54:47 +0300
commit36f8960de887a5e2811c5d1c0517cfa6f419c1c4 (patch)
tree64ee3eadd60d16062983445e53366aa91bd0600b /Documentation/arch
parent2467c2104f1fd4be1f0c415054b1d91f75fbe562 (diff)
downloadlinux-36f8960de887a5e2811c5d1c0517cfa6f419c1c4.tar.xz
riscv: hwprobe: export Zimop ISA extension
Export Zimop ISA extension through hwprobe. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20240619113529.676940-4-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/arch')
-rw-r--r--Documentation/arch/riscv/hwprobe.rst4
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index fc015b452ebf..2b7f1d05b2e3 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -207,6 +207,10 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is
+ supported as defined in the RISC-V ISA manual starting from commit
+ 58220614a5f ("Zimop is ratified/1.0").
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.