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| author | Emil Renner Berthing <kernel@esmil.dk> | 2021-11-20 23:33:08 +0300 |
|---|---|---|
| committer | Emil Renner Berthing <kernel@esmil.dk> | 2022-07-13 00:26:02 +0300 |
| commit | 5eb6741c2e89b4e9f86d6b9daaf08085197ea83c (patch) | |
| tree | 6d02993524a9c8346708e6250ae74f73f4f518dd | |
| parent | 07a6b2e41bf51fe66f482cb62af36b085bb87de9 (diff) | |
| download | linux-5eb6741c2e89b4e9f86d6b9daaf08085197ea83c.tar.xz | |
RISC-V: Add StarFive JH7100 audio reset node
Add device tree node for the audio resets on the StarFive JH7100 RISC-V
SoC.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 891c3acf5641..247e3864d204 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -131,6 +131,12 @@ #clock-cells = <1>; }; + audrst: reset-controller@10490000 { + compatible = "starfive,jh7100-audrst"; + reg = <0x0 0x10490000 0x0 0x10000>; + #reset-cells = <1>; + }; + clkgen: clock-controller@11800000 { compatible = "starfive,jh7100-clkgen"; reg = <0x0 0x11800000 0x0 0x10000>; |