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| author | xingyu.wu <xingyu.wu@starfivetech.com> | 2022-03-07 06:12:19 +0300 |
|---|---|---|
| committer | Andy Hu <andy.hu@starfivetech.com> | 2022-03-23 19:49:56 +0300 |
| commit | 965e897cefd13cf5564970972ad5b3ce876b8d10 (patch) | |
| tree | eb5f448a51efc8a5613dfb8ff5d325dd8fe1ce29 | |
| parent | f1f103e8263bb7a065ea2583fa0cf53092dcf5a6 (diff) | |
| download | linux-965e897cefd13cf5564970972ad5b3ce876b8d10.tar.xz | |
dts/starfive/jh7100.dtsi:Amend JPU module device tree
Add clocks and resets in JPU module device tree.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100.dtsi | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 5b233f74bfc5..d531c6c12951 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -672,8 +672,16 @@ compatible = "cm,codaj12-jpu-1"; reg = <0x0 0x11900000 0x0 0x300>; reg-names = "control"; - clocks = <&clkgen JH7100_CLK_JPEG_APB>; - clock-names = "jpege"; + clocks = <&clkgen JH7100_CLK_JPEG_AXI>, + <&clkgen JH7100_CLK_JPEG_CCLK>, + <&clkgen JH7100_CLK_JPEG_APB>, + <&clkgen JH7100_CLK_VDECBRG_MAIN>, + <&clkgen JH7100_CLK_JPCGC300_MAIN>; + clock-names = "jpeg_axi", "jpeg_cclk", "jpeg_apb", "vdecbrg_main", "jpcgc300_main"; + resets = <&rstgen JH7100_RSTN_JPEG_AXI>, + <&rstgen JH7100_RSTN_JPEG_CCLK>, + <&rstgen JH7100_RSTN_JPEG_APB>; + reset-names = "jpeg_axi", "jpeg_cclk", "jpeg_apb"; interrupts = <24>; memory-region = <&jpu_reserved>; }; |