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| author | Clément Léger <cleger@rivosinc.com> | 2024-04-09 17:38:37 +0300 |
|---|---|---|
| committer | Ji Sheng Teoh <jisheng.teoh@starfivetech.com> | 2025-01-13 09:07:52 +0300 |
| commit | 500653e6f866bf01fce9ea80ab2bd3069ea92fb9 (patch) | |
| tree | 68dfa665a4beb5c6f90665947f084b184b2bcd6b | |
| parent | 022ef092212917073869766a6fbd58a7469e1d20 (diff) | |
| download | linux-500653e6f866bf01fce9ea80ab2bd3069ea92fb9.tar.xz | |
riscv: hwprobe: fix invalid sign extension for RISCV_HWPROBE_EXT_ZVFHMIN
The current definition yields a negative 32bits signed value which
result in a mask with is obviously incorrect. Replace it by using a
1ULL bit shift value to obtain a single set bit mask.
Fixes: 5dadda5e6a59 ("riscv: hwprobe: export Zvfh[min] ISA extensions")
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20240409143839.558784-1-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | arch/riscv/include/uapi/asm/hwprobe.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index c1f8b787fff3..920003040f3d 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -54,7 +54,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28) #define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29) #define RISCV_HWPROBE_EXT_ZVFH (1 << 30) -#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) +#define RISCV_HWPROBE_EXT_ZVFHMIN (1ULL << 31) #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) |