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| author | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2024-01-22 06:25:42 +0300 |
|---|---|---|
| committer | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2024-01-22 08:09:51 +0300 |
| commit | c0a8c322b65c1120f2872ee28072adfdd8d7ff0a (patch) | |
| tree | 4d5fd0060dba3183ac3425cf341f9c5c68dc204a | |
| parent | abcde1d6be11eddd60118dfaecb9a2332536d2f2 (diff) | |
| download | linux-c0a8c322b65c1120f2872ee28072adfdd8d7ff0a.tar.xz | |
riscv: dts: starfive: dubhe: Update CPU isa-extensions
Fix DT binding check errors. Change "b" to "zba", "zbb", "zbc" and "zbs".
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
| -rwxr-xr-x | arch/riscv/boot/dts/starfive/dubhe.dtsi | 10 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe70.dtsi | 16 |
2 files changed, 14 insertions, 12 deletions
diff --git a/arch/riscv/boot/dts/starfive/dubhe.dtsi b/arch/riscv/boot/dts/starfive/dubhe.dtsi index 2e790666733b..d87f7ac08ea5 100755 --- a/arch/riscv/boot/dts/starfive/dubhe.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe.dtsi @@ -18,8 +18,9 @@ reg = <0x0>; riscv,isa = "rv64imafdcbh"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", - "zicntr", "zicsr", "zifencei", "zihpm", "sscofpmf"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicntr", "zicsr", "zifencei", + "zihpm", "sscofpmf"; tlb-split; cpu0_intc: interrupt-controller { @@ -36,8 +37,9 @@ reg = <0x1>; riscv,isa = "rv64imafdcbh"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", - "zicntr", "zicsr", "zifencei", "zihpm", "sscofpmf"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicntr", "zicsr", "zifencei", + "zihpm", "sscofpmf"; tlb-split; cpu1_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/starfive/dubhe70.dtsi b/arch/riscv/boot/dts/starfive/dubhe70.dtsi index 81cddf3fe0e3..b9dad5cbb376 100644 --- a/arch/riscv/boot/dts/starfive/dubhe70.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe70.dtsi @@ -7,10 +7,10 @@ compatible = "starfive,dubhe-70", "riscv"; riscv,isa = "rv64imafdcbh"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zicbom", - "zicboz", "zicntr", "zicond", "zicsr", "zifencei", - "zihintpause", "zihpm", "svinval", "svnapot", "svpbmt", - "sscofpmf"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; riscv,cbom-block-size = <64>; riscv,cboz-block-size = <64>; d-cache-block-size = <64>; @@ -30,10 +30,10 @@ compatible = "starfive,dubhe-70", "riscv"; riscv,isa = "rv64imafdcbh"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zicbom", - "zicboz", "zicntr", "zicond", "zicsr", "zifencei", - "zihintpause", "zihpm", "svinval", "svnapot", "svpbmt", - "sscofpmf"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zba", "zbb", + "zbc", "zbs", "zicbom", "zicboz", "zicntr", + "zicond", "zicsr", "zifencei", "zihintpause", + "zihpm", "svinval", "svnapot", "svpbmt", "sscofpmf"; riscv,cbom-block-size = <64>; riscv,cboz-block-size = <64>; d-cache-block-size = <64>; |