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| author | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2024-01-16 11:19:00 +0300 |
|---|---|---|
| committer | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2024-01-22 08:09:51 +0300 |
| commit | abcde1d6be11eddd60118dfaecb9a2332536d2f2 (patch) | |
| tree | de056ef2c62542177cbdbf2e11eb063dbceb6bba | |
| parent | c8032bbb95e372cc85252422f30c0d0e5bd06b5a (diff) | |
| download | linux-abcde1d6be11eddd60118dfaecb9a2332536d2f2.tar.xz | |
riscv: dts: starfive: dubhe: Update L2 DT node
Dubhe-80 and Dubhe-70 use private L2, Dubhe-90 uses shared L2.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
| -rwxr-xr-x | arch/riscv/boot/dts/starfive/dubhe.dtsi | 12 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe70.dtsi | 12 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe80.dtsi | 12 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe90.dtsi | 8 |
4 files changed, 37 insertions, 7 deletions
diff --git a/arch/riscv/boot/dts/starfive/dubhe.dtsi b/arch/riscv/boot/dts/starfive/dubhe.dtsi index 5ec30a7d9423..2e790666733b 100755 --- a/arch/riscv/boot/dts/starfive/dubhe.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe.dtsi @@ -15,7 +15,6 @@ cpu0: cpu@0 { device_type = "cpu"; mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache>; reg = <0x0>; riscv,isa = "rv64imafdcbh"; riscv,isa-base = "rv64i"; @@ -34,7 +33,6 @@ compatible = "starfive,dubhe", "riscv"; device_type = "cpu"; mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache>; reg = <0x1>; riscv,isa = "rv64imafdcbh"; riscv,isa-base = "rv64i"; @@ -61,15 +59,19 @@ }; }; - l2_cache: cache-controller { + l2_cache0: cache-controller-0 { compatible = "cache"; cache-block-size = <64>; cache-level = <2>; - cache-sets = <4096>; - cache-size = <0x200000>; cache-unified; }; + l2_cache1: cache-controller-1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-unified; + }; }; pmu { diff --git a/arch/riscv/boot/dts/starfive/dubhe70.dtsi b/arch/riscv/boot/dts/starfive/dubhe70.dtsi index 8060e0f2ad5b..81cddf3fe0e3 100644 --- a/arch/riscv/boot/dts/starfive/dubhe70.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe70.dtsi @@ -23,6 +23,7 @@ i-cache-size = <32768>; i-tlb-sets = <1>; i-tlb-size = <24>; + next-level-cache = <&l2_cache0>; }; &cpu1 { @@ -45,4 +46,15 @@ i-cache-size = <32768>; i-tlb-sets = <1>; i-tlb-size = <24>; + next-level-cache = <&l2_cache1>; +}; + +&l2_cache0 { + cache-sets = <2048>; + cache-size = <0x20000>; +}; + +&l2_cache1 { + cache-sets = <2048>; + cache-size = <0x20000>; }; diff --git a/arch/riscv/boot/dts/starfive/dubhe80.dtsi b/arch/riscv/boot/dts/starfive/dubhe80.dtsi index 5f6a760ee206..9031457ac7de 100644 --- a/arch/riscv/boot/dts/starfive/dubhe80.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe80.dtsi @@ -15,6 +15,7 @@ i-cache-size = <32768>; i-tlb-sets = <1>; i-tlb-size = <48>; + next-level-cache = <&l2_cache0>; }; &cpu1 { @@ -29,8 +30,17 @@ i-cache-size = <32768>; i-tlb-sets = <1>; i-tlb-size = <48>; + next-level-cache = <&l2_cache1>; }; -&l2_cache { +&l2_cache0 { compatible = "starfive,dubhe-cache", "cache"; + cache-sets = <512>; + cache-size = <0x40000>; +}; + +&l2_cache1 { + compatible = "starfive,dubhe-cache", "cache"; + cache-sets = <512>; + cache-size = <0x40000>; }; diff --git a/arch/riscv/boot/dts/starfive/dubhe90.dtsi b/arch/riscv/boot/dts/starfive/dubhe90.dtsi index a89dcd8ca70e..b75f2b0c1026 100644 --- a/arch/riscv/boot/dts/starfive/dubhe90.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe90.dtsi @@ -15,6 +15,7 @@ i-cache-size = <65536>; i-tlb-sets = <1>; i-tlb-size = <48>; + next-level-cache = <&l2_cache0>; }; &cpu1 { @@ -29,8 +30,13 @@ i-cache-size = <65536>; i-tlb-sets = <1>; i-tlb-size = <48>; + next-level-cache = <&l2_cache0>; }; -&l2_cache { +&l2_cache0 { compatible = "starfive,dubhe-cache", "cache"; + cache-sets = <4096>; + cache-size = <0x200000>; }; + +/delete-node/ &l2_cache1; |