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| author | Guo Ren <guoren@linux.alibaba.com> | 2023-12-31 11:29:52 +0300 |
|---|---|---|
| committer | Ji Sheng Teoh <jisheng.teoh@starfivetech.com> | 2024-02-21 05:00:48 +0300 |
| commit | a7074873b0a164e4defb8a664007c76988419f3c (patch) | |
| tree | b2e95836a77c21ecbd689580b25bc08f265a84f5 | |
| parent | 917bc92ac1da11c9cbc58c7a7cd89453a6e583bc (diff) | |
| download | linux-a7074873b0a164e4defb8a664007c76988419f3c.tar.xz | |
riscv: Add ARCH_HAS_PRETCHW support with Zicbop
Enable Linux prefetchw primitive with Zicbop cpufeature, which preloads
cache line into L1 cache for the next write operation.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
| -rw-r--r-- | arch/riscv/include/asm/processor.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 3e23e1786d05..69be17365f2f 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -12,6 +12,8 @@ #include <vdso/processor.h> #include <asm/ptrace.h> +#include <asm/insn-def.h> +#include <asm/alternative-macros.h> #ifdef CONFIG_64BIT #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1)) @@ -103,6 +105,20 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset, #define KSTK_EIP(tsk) (task_pt_regs(tsk)->epc) #define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp) +#ifdef CONFIG_RISCV_ISA_ZICBOP +#define ARCH_HAS_PREFETCHW +#define RISCV_ISA_EXT_ZICBOP 45 + +#define PREFETCHW_ASM(x) \ + ALTERNATIVE(__nops(1), CBO_PREFETCH_W(x, 0), 0, \ + RISCV_ISA_EXT_ZICBOP, CONFIG_RISCV_ISA_ZICBOP) + + +static inline void prefetchw(const void *x) +{ + __asm__ __volatile__(PREFETCHW_ASM(%0) : : "r" (x) : "memory"); +} +#endif /* CONFIG_RISCV_ISA_ZICBOP */ /* Do necessary setup to start up a newly executed thread. */ extern void start_thread(struct pt_regs *regs, |