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| author | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2023-11-15 17:48:44 +0300 |
|---|---|---|
| committer | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2024-01-08 10:49:13 +0300 |
| commit | 96d6321bc569d6cc6838ae5f0bbe92a1e44f5f4a (patch) | |
| tree | 6d6a9ba5dd30d794948d33d652e5d2aed84f3837 | |
| parent | 4bd61367515d6b4125ac0516bb47f5e27bbd52e7 (diff) | |
| download | linux-96d6321bc569d6cc6838ae5f0bbe92a1e44f5f4a.tar.xz | |
riscv: dts: starfive: dubhe: Update Dubhe CPU compatible strings
Change to "starfive,dubhe-80" and "starfive,dubhe-90" compatible strings.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
| -rwxr-xr-x | arch/riscv/boot/dts/starfive/dubhe.dtsi | 1 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe80.dtsi | 2 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe90.dtsi | 2 |
3 files changed, 4 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/starfive/dubhe.dtsi b/arch/riscv/boot/dts/starfive/dubhe.dtsi index aa172bd6740a..0ca083287d3f 100755 --- a/arch/riscv/boot/dts/starfive/dubhe.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe.dtsi @@ -13,7 +13,6 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "starfive,dubhe", "riscv"; device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache>; diff --git a/arch/riscv/boot/dts/starfive/dubhe80.dtsi b/arch/riscv/boot/dts/starfive/dubhe80.dtsi index 32bef3345bd6..5f6a760ee206 100644 --- a/arch/riscv/boot/dts/starfive/dubhe80.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe80.dtsi @@ -4,6 +4,7 @@ #include "dubhe.dtsi" &cpu0 { + compatible = "starfive,dubhe-80", "riscv"; d-cache-block-size = <64>; d-cache-sets = <512>; d-cache-size = <32768>; @@ -17,6 +18,7 @@ }; &cpu1 { + compatible = "starfive,dubhe-80", "riscv"; d-cache-block-size = <64>; d-cache-sets = <512>; d-cache-size = <32768>; diff --git a/arch/riscv/boot/dts/starfive/dubhe90.dtsi b/arch/riscv/boot/dts/starfive/dubhe90.dtsi index e243f3387336..a89dcd8ca70e 100644 --- a/arch/riscv/boot/dts/starfive/dubhe90.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe90.dtsi @@ -4,6 +4,7 @@ #include "dubhe.dtsi" &cpu0 { + compatible = "starfive,dubhe-90", "riscv"; d-cache-block-size = <64>; d-cache-sets = <1024>; d-cache-size = <65536>; @@ -17,6 +18,7 @@ }; &cpu1 { + compatible = "starfive,dubhe-90", "riscv"; d-cache-block-size = <64>; d-cache-sets = <1024>; d-cache-size = <65536>; |