diff options
| author | Ji Sheng Teoh <jisheng.teoh@starfivetech.com> | 2024-01-11 09:19:15 +0300 |
|---|---|---|
| committer | Ji Sheng Teoh <jisheng.teoh@starfivetech.com> | 2024-01-16 12:58:10 +0300 |
| commit | 77310137ef1e673bd5c376a9503b304a25d25226 (patch) | |
| tree | df19c6df59d590ec1ec58f88127f3cae8aad2666 | |
| parent | 5397d136a7fe0e78a6f20e2340a37aa8f9241e5e (diff) | |
| download | linux-77310137ef1e673bd5c376a9503b304a25d25226.tar.xz | |
riscv: dts: starfive: Convert to riscv,isa-base and riscv,isa-extensions
Update StarFive's Dubhe80 and Dubhe90 device tree to use riscv,isa-base
and riscv,extensions property to express RISC-V profiles and extensions
supported by the platforms.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
| -rwxr-xr-x | arch/riscv/boot/dts/starfive/dubhe.dtsi | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/starfive/dubhe.dtsi b/arch/riscv/boot/dts/starfive/dubhe.dtsi index 580eea819f4d..5ec30a7d9423 100755 --- a/arch/riscv/boot/dts/starfive/dubhe.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe.dtsi @@ -17,7 +17,10 @@ mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache>; reg = <0x0>; - riscv,isa = "rv64imafdcbh_sscofpmf"; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zicntr", "zicsr", "zifencei", "zihpm", "sscofpmf"; tlb-split; cpu0_intc: interrupt-controller { @@ -33,7 +36,10 @@ mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache>; reg = <0x1>; - riscv,isa = "rv64imafdcbh_sscofpmf"; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", + "zicntr", "zicsr", "zifencei", "zihpm", "sscofpmf"; tlb-split; cpu1_intc: interrupt-controller { |