diff options
| author | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2023-11-15 20:36:57 +0300 |
|---|---|---|
| committer | Ley Foon Tan <leyfoon.tan@starfivetech.com> | 2024-01-08 10:49:13 +0300 |
| commit | 5a94e10196a29849811214e66dc92470b97c75bf (patch) | |
| tree | ab9ecca76110cfeb4d9904f0045d1cd24fcff7b7 | |
| parent | 3fc326fff6c1658017519a1076b486f7f8b147f8 (diff) | |
| download | linux-5a94e10196a29849811214e66dc92470b97c75bf.tar.xz | |
riscv: dts: starfive: dubhe: Move pmu DT node out of soc node
PMU hardware is in the CPU core, move the pmu DT node out of the soc node.
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
| -rwxr-xr-x | arch/riscv/boot/dts/starfive/dubhe.dtsi | 81 |
1 files changed, 40 insertions, 41 deletions
diff --git a/arch/riscv/boot/dts/starfive/dubhe.dtsi b/arch/riscv/boot/dts/starfive/dubhe.dtsi index 1735cc6f6f08..580eea819f4d 100755 --- a/arch/riscv/boot/dts/starfive/dubhe.dtsi +++ b/arch/riscv/boot/dts/starfive/dubhe.dtsi @@ -66,6 +66,46 @@ }; + pmu { + compatible = "riscv,pmu"; + interrupts-extended = <&cpu0_intc 13>, <&cpu1_intc 13>; + riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>, + <0x00006 0x0000 0xB>, + <0x00008 0x0000 0x10>, + <0x00009 0x0000 0xF>, + <0x10000 0x0000 0x19>, + <0x10001 0x0000 0x1A>, + <0x10002 0x0000 0x1B>, + <0x10003 0x0000 0x1C>, + <0x10008 0x0000 0x8>, + <0x10009 0x0000 0x9>, + <0x1000C 0x0000 0x9E>, + <0x1000D 0x0000 0x9F>, + <0x10010 0x0000 0x1D>, + <0x10011 0x0000 0x1E>, + <0x10012 0x0000 0x1F>, + <0x10013 0x0000 0x20>, + <0x10014 0x0000 0x21>, + <0x10018 0x0000 0x17>, + <0x10019 0x0000 0x18>, + <0x10020 0x0000 0x8>, + <0x10021 0x0000 0x7>; + + riscv,event-to-mhpmcounters = <0x00005 0x00006 0x00007FF8>, + <0x00008 0x00009 0x00007FF8>, + <0x10000 0x10003 0x00007FF8>, + <0x10008 0x10009 0x00007FF8>, + <0x1000C 0x1000D 0x00007FF8>, + <0x10010 0x10014 0x00007FF8>, + <0x10018 0x10019 0x00007FF8>, + <0x10020 0x10021 0x00007FF8>; + + riscv,raw-event-to-mhpmcounters = + <0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>, /* Event ID 1-31 */ + <0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>, /* Event ID 32-33 */ + <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */ + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -167,46 +207,5 @@ snps,rxpbl = <4>; status = "disabled"; }; - - pmu { - compatible = "riscv,pmu"; - interrupts-extended = <&cpu0_intc 13>, - <&cpu1_intc 13>; - riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>, - <0x00006 0x0000 0xB>, - <0x00008 0x0000 0x10>, - <0x00009 0x0000 0xF>, - <0x10000 0x0000 0x19>, - <0x10001 0x0000 0x1A>, - <0x10002 0x0000 0x1B>, - <0x10003 0x0000 0x1C>, - <0x10008 0x0000 0x8>, - <0x10009 0x0000 0x9>, - <0x1000C 0x0000 0x9E>, - <0x1000D 0x0000 0x9F>, - <0x10010 0x0000 0x1D>, - <0x10011 0x0000 0x1E>, - <0x10012 0x0000 0x1F>, - <0x10013 0x0000 0x20>, - <0x10014 0x0000 0x21>, - <0x10018 0x0000 0x17>, - <0x10019 0x0000 0x18>, - <0x10020 0x0000 0x8>, - <0x10021 0x0000 0x7>; - - riscv,event-to-mhpmcounters = <0x00005 0x00006 0x00007FF8>, - <0x00008 0x00009 0x00007FF8>, - <0x10000 0x10003 0x00007FF8>, - <0x10008 0x10009 0x00007FF8>, - <0x1000C 0x1000D 0x00007FF8>, - <0x10010 0x10014 0x00007FF8>, - <0x10018 0x10019 0x00007FF8>, - <0x10020 0x10021 0x00007FF8>; - - riscv,raw-event-to-mhpmcounters = - <0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>, /* Event ID 1-31 */ - <0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>, /* Event ID 32-33 */ - <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */ - }; }; }; |