diff options
author | Ji Sheng Teoh <jisheng.teoh@starfivetech.com> | 2024-01-12 12:03:24 +0300 |
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committer | Ji Sheng Teoh <jisheng.teoh@starfivetech.com> | 2024-01-16 12:58:20 +0300 |
commit | 30387e227506433af5072cebac0727751a7e87e1 (patch) | |
tree | 44f9e992f84c7d60f396f7d9e6e124856154187d | |
parent | 77310137ef1e673bd5c376a9503b304a25d25226 (diff) | |
download | linux-30387e227506433af5072cebac0727751a7e87e1.tar.xz |
perf vendor events riscv: starfive: add RISC-V firmware JSON file
Add standard RISC-V firmware events to support monitoring of firmware
events in StarFive's Dubhe platform.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
-rw-r--r-- | tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json new file mode 100644 index 000000000000..37079ebe9316 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json @@ -0,0 +1,68 @@ +[ + { + "ArchStdEvent": "FW_MISALIGNED_LOAD" + }, + { + "ArchStdEvent": "FW_MISALIGNED_STORE" + }, + { + "ArchStdEvent": "FW_ACCESS_LOAD" + }, + { + "ArchStdEvent": "FW_ACCESS_STORE" + }, + { + "ArchStdEvent": "FW_ILLEGAL_INSN" + }, + { + "ArchStdEvent": "FW_SET_TIMER" + }, + { + "ArchStdEvent": "FW_IPI_SENT" + }, + { + "ArchStdEvent": "FW_IPI_RECEIVED" + }, + { + "ArchStdEvent": "FW_FENCE_I_SENT" + }, + { + "ArchStdEvent": "FW_FENCE_I_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_SENT" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED" + } +]
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