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| author | Ji Sheng Teoh <jisheng.teoh@starfivetech.com> | 2023-12-28 04:41:43 +0300 |
|---|---|---|
| committer | Ji Sheng Teoh <jisheng.teoh@starfivetech.com> | 2024-01-16 12:57:55 +0300 |
| commit | 0da7a2e4f31baf99c3224953ac225ce2f1c9091b (patch) | |
| tree | bedfffdbb6958b8bf7ed73a1ca51e9209cfd58f1 | |
| parent | ad276995b16596340b8f4c0ab906ac82ee6b09d1 (diff) | |
| download | linux-0da7a2e4f31baf99c3224953ac225ce2f1c9091b.tar.xz | |
riscv: dts: starfive: Add StarFive Dubhe-70 device tree
Add device tree support for StarFive's Dubhe-70.
Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/Makefile | 1 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe70.dtsi | 48 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/dubhe70_fpga.dts | 5 |
3 files changed, 54 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index a8a97301e8fa..aab2781fbc76 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -14,3 +14,4 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_ARCH_STARFIVE) += dubhe90_fpga.dtb dtb-$(CONFIG_ARCH_STARFIVE) += dubhe90_fpga_dual.dtb dtb-$(CONFIG_ARCH_STARFIVE) += dubhe80_fpga.dtb +dtb-$(CONFIG_ARCH_STARFIVE) += dubhe70_fpga.dtb diff --git a/arch/riscv/boot/dts/starfive/dubhe70.dtsi b/arch/riscv/boot/dts/starfive/dubhe70.dtsi new file mode 100644 index 000000000000..8060e0f2ad5b --- /dev/null +++ b/arch/riscv/boot/dts/starfive/dubhe70.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2023 StarFive Technology Co., Ltd. */ + +#include "dubhe.dtsi" + +&cpu0 { + compatible = "starfive,dubhe-70", "riscv"; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zicbom", + "zicboz", "zicntr", "zicond", "zicsr", "zifencei", + "zihintpause", "zihpm", "svinval", "svnapot", "svpbmt", + "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <16>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <24>; +}; + +&cpu1 { + compatible = "starfive,dubhe-70", "riscv"; + riscv,isa = "rv64imafdcbh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zicbom", + "zicboz", "zicntr", "zicond", "zicsr", "zifencei", + "zihintpause", "zihpm", "svinval", "svnapot", "svpbmt", + "sscofpmf"; + riscv,cbom-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <16>; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <24>; +}; diff --git a/arch/riscv/boot/dts/starfive/dubhe70_fpga.dts b/arch/riscv/boot/dts/starfive/dubhe70_fpga.dts new file mode 100644 index 000000000000..a4e9ea608cb8 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/dubhe70_fpga.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2023 StarFive Technology Co., Ltd. */ + +#include "dubhe70.dtsi" +#include "dubhe_fpga_common.dtsi" |