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authorLey Foon Tan <leyfoon.tan@linux.starfivetech.com>2022-07-21 09:42:41 +0300
committerLey Foon Tan <leyfoon.tan@starfivetech.com>2023-12-04 06:00:12 +0300
commitda33f32aa433dcf26f3c8cb696735f6dd738b0b7 (patch)
tree523fa65f724bb49ba84da71a709bde1d700260f6
parente6d46b5cdacd78989ab3e9e04d67a8dbc224cacb (diff)
downloadlinux-da33f32aa433dcf26f3c8cb696735f6dd738b0b7.tar.xz
riscv: dts: starfive: dubhe: Add GMAC DT node
This patch adds GMAC device tree node. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
-rw-r--r--arch/riscv/boot/dts/starfive/dubhe.dtsi34
-rw-r--r--arch/riscv/boot/dts/starfive/dubhe_fpga.dts24
2 files changed, 58 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/dubhe.dtsi b/arch/riscv/boot/dts/starfive/dubhe.dtsi
index 73e0090fb7b1..a0506d46134a 100644
--- a/arch/riscv/boot/dts/starfive/dubhe.dtsi
+++ b/arch/riscv/boot/dts/starfive/dubhe.dtsi
@@ -124,6 +124,40 @@
status = "disabled";
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <256 128 64 32 0 0 0>;
+ };
+
+ gmac0: gmac@10100000 {
+ compatible = "starfive,dwmac","snps,dwmac-5.10a";
+ reg = <0x0 0x10100000 0x0 0x10000>;
+ clock-names = "gtx",
+ "tx",
+ "ptp_ref",
+ "stmmaceth",
+ "pclk",
+ "gtxc";
+ interrupt-parent = <&plic0>;
+ interrupts = <8>, <11>, <12>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ max-frame-size = <1500>;
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <8>;
+ rx-fifo-depth = <2048>;
+ tx-fifo-depth = <2048>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,tso;
+ snps,en-tx-lpi-clockgating;
+ snps,txpbl = <4>;
+ snps,rxpbl = <4>;
+ status = "disabled";
+ };
+
pmu {
compatible = "riscv,pmu";
riscv,event-to-mhpmevent = <0x00005 0x0000 0x1B>,
diff --git a/arch/riscv/boot/dts/starfive/dubhe_fpga.dts b/arch/riscv/boot/dts/starfive/dubhe_fpga.dts
index dce02d6ccd96..5ff774ffe816 100644
--- a/arch/riscv/boot/dts/starfive/dubhe_fpga.dts
+++ b/arch/riscv/boot/dts/starfive/dubhe_fpga.dts
@@ -7,6 +7,7 @@
model = "StarFive Dubhe FPGA";
aliases {
+ ethernet0 = &gmac0;
serial0 = &uart0;
};
@@ -25,9 +26,32 @@
};
soc {
+
+ fpga_2p5mhz_clk: fpga_2p5mhz_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500000>;
+ };
+
+ fpga_50mhz_clk: fpga_50mhz_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
};
};
+&gmac0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ clocks = <&fpga_2p5mhz_clk>,
+ <&fpga_2p5mhz_clk>,
+ <&fpga_2p5mhz_clk>,
+ <&fpga_50mhz_clk>,
+ <&fpga_50mhz_clk>,
+ <&fpga_2p5mhz_clk>;
+};
+
&spi0 {
status = "okay";
mmc@0 {