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| author | Minda Chen <minda.chen@starfivetech.com> | 2023-11-09 05:05:47 +0300 |
|---|---|---|
| committer | Minda Chen <minda.chen@starfivetech.com> | 2023-12-22 06:27:40 +0300 |
| commit | 982362719a6c83c192c4aa0166f177772ba4b2fa (patch) | |
| tree | 856ea3b9ed902fd7d459e59481c4eb7fd5bceb34 | |
| parent | 06ad134b6efeb393868e300058752ecfbf7258d1 (diff) | |
| download | linux-982362719a6c83c192c4aa0166f177772ba4b2fa.tar.xz | |
dts: jh7110: disable cpu4 and reserve memory for rtthread
disable cpu4 to run rt-thread and rerserve heap memory
for rtthread.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi | 8 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 6 |
2 files changed, 13 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi index 31f0448f360e..b0aed338088d 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi @@ -71,6 +71,9 @@ reg = <0x0 0x69c00000 0x0 0x03001000>; }; + rtthread_reserved: rt@6e400000 { + reg = <0x0 0x6e400000 0x0 0x1c00000>; + }; }; leds { @@ -953,6 +956,11 @@ memory-region = <&hifi4_reserved>; }; +&rtthread { + memory-region = <&rtthread_reserved>; + status = "okay"; +}; + &qspi { nor_flash: nor-flash@0 { compatible = "jedec,spi-nor"; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 134a2c1c8df5..8511ae22ce78 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -218,7 +218,7 @@ riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; #cooling-cells = <2>; - status = "okay"; + status = "disabled"; operating-points-v2 = <&cluster0_opp>; cpu4intctrl: interrupt-controller { @@ -1822,6 +1822,10 @@ status = "disabled"; }; + rtthread: rtthread@0 { + compatible = "starfive,rtthread"; + }; + starfive_cpufreq: starfive,jh7110-cpufreq { compatible = "starfive,jh7110-cpufreq"; clocks = <&clkgen JH7110_CPU_CORE>; |