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| author | Andy Hu <andy.hu@starfivetech.com> | 2023-09-01 06:36:27 +0300 |
|---|---|---|
| committer | Andy Hu <andy.hu@starfivetech.com> | 2023-09-01 06:36:27 +0300 |
| commit | d1ff698066686acd73d236b74976972837f2d883 (patch) | |
| tree | ec5b431c51d213f9ea63785fa2fe887405dbeab8 | |
| parent | eb60040147458556ecf7c2212074a639dba19c4e (diff) | |
| parent | 500bb669cd1cc7f42b21567b4083a5410948a004 (diff) | |
| download | linux-d1ff698066686acd73d236b74976972837f2d883.tar.xz | |
Merge tag 'JH7110_515_SDK_v5.7.1' into vf2-515-devel
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index a2831f719bca..e5d0445767f1 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -635,7 +635,7 @@ clocks = <&clkgen JH7110_DMA1P_CLK_AXI>, <&clkgen JH7110_DMA1P_CLK_AHB>, <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>; - clock-names = "core-clk", "cfgr-clk", "stg_clk"; + clock-names = "core-clk", "cfgr-clk", "noc-clk"; resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>, <&rstgen RSTN_U0_DW_DMA1P_AHB>, <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>; |