summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDimitry Andric <dimitry.andric@tomtom.com>2005-07-26 22:20:25 +0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-07-26 22:20:25 +0400
commit02cdad3f932d533e5cbde1b15092418ce7af1a70 (patch)
treeb7bf8988093e11032c73a54e02f05f4e20f4288e
parent6b6a93c6876ea1c530d5d3f68e3678093a27fab0 (diff)
downloadlinux-02cdad3f932d533e5cbde1b15092418ce7af1a70.tar.xz
[PATCH] ARM: 2819/1: Fix several S3C24x0 IIS defines
Patch from Dimitry Andric - Change S3C2440_IISCON_MPLL to S3C2440_IISMOD_MPLL: The S3C2440 IISCON register doesn\'t control the master clock selection, this is done with the IISMOD register. - Correct S3C2410_IISMOD_256FS and S3C2410_IISMOD_384FS: This is set via bit 2 of IISMOD, not bit 1. - Add S3C2410_IISCON_PSCEN (prescaler enable), for completeness\' sake. Signed-off-by: Dimitry Andric <dimitry.andric@tomtom.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--include/asm-arm/arch-s3c2410/regs-iis.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
index 385b07d510da..fdd62e8cd6cb 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -15,6 +15,9 @@
* 12-03-2004 BJD Updated include protection
* 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL
* 05-04-2005 LCVR Added IISFCON definitions for the S3C2400
+ * 18-07-2005 DA Change IISCON_MPLL to IISMOD_MPLL
+ * Correct IISMOD_256FS and IISMOD_384FS
+ * Add IISCON_PSCEN
*/
#ifndef __ASM_ARCH_REGS_IIS_H
@@ -22,7 +25,6 @@
#define S3C2410_IISCON (0x00)
-#define S3C2440_IISCON_MPLL (1<<9)
#define S3C2410_IISCON_LRINDEX (1<<8)
#define S3C2410_IISCON_TXFIFORDY (1<<7)
#define S3C2410_IISCON_RXFIFORDY (1<<6)
@@ -30,10 +32,12 @@
#define S3C2410_IISCON_RXDMAEN (1<<4)
#define S3C2410_IISCON_TXIDLE (1<<3)
#define S3C2410_IISCON_RXIDLE (1<<2)
+#define S3C2410_IISCON_PSCEN (1<<1)
#define S3C2410_IISCON_IISEN (1<<0)
#define S3C2410_IISMOD (0x04)
+#define S3C2440_IISMOD_MPLL (1<<9)
#define S3C2410_IISMOD_SLAVE (1<<8)
#define S3C2410_IISMOD_NOXFER (0<<6)
#define S3C2410_IISMOD_RXMODE (1<<6)
@@ -46,8 +50,8 @@
#define S3C2410_IISMOD_8BIT (0<<3)
#define S3C2410_IISMOD_16BIT (1<<3)
#define S3C2410_IISMOD_BITMASK (1<<3)
-#define S3C2410_IISMOD_256FS (0<<1)
-#define S3C2410_IISMOD_384FS (1<<1)
+#define S3C2410_IISMOD_256FS (0<<2)
+#define S3C2410_IISMOD_384FS (1<<2)
#define S3C2410_IISMOD_16FS (0<<0)
#define S3C2410_IISMOD_32FS (1<<0)
#define S3C2410_IISMOD_48FS (2<<0)