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authorBen Skeggs <bskeggs@redhat.com>2010-01-18 01:33:04 +0300
committerBen Skeggs <bskeggs@redhat.com>2010-01-18 02:56:19 +0300
commit134f248bea4bf5c3169b4950eb49c6651b09eb0e (patch)
treedb66d0ce739c94538603f491017063c0ac8e0413
parent71666475018a3024fb49499096d26a9350349e8b (diff)
downloadlinux-134f248bea4bf5c3169b4950eb49c6651b09eb0e.tar.xz
drm/nv50: fix alignment of per-channel fifo cache
GPU pointer to the structure is shifted right by 10 bits, so we need to align to 1024 bytes, not 256. Reported-by: Maarten Maathuis <madman2003@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fifo.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index 39caf167587d..32b244bcb482 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -272,7 +272,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
return ret;
ramfc = chan->ramfc->gpuobj;
- ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 256,
+ ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 1024,
0, &chan->cache);
if (ret)
return ret;