diff options
author | Joseph Gravenor <joseph.gravenor@amd.com> | 2019-11-13 01:48:36 +0300 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2019-12-06 00:30:50 +0300 |
commit | e0600a94343cc772b33705015cb8c05bac32bccb (patch) | |
tree | ce5d6e3f4063aa7c8a64e95227d6dd93117b0cdc | |
parent | 2f39835cc35033672ace41f32d653dbf2c0c8132 (diff) | |
download | linux-e0600a94343cc772b33705015cb8c05bac32bccb.tar.xz |
drm/amd/display: update sr latency for renoir when using lpddr4
[Why]
DF team has produced more optimized sr latency numbers, for lpddr4
[How]
change the sr laency in the lpddr4 wm table to the new latency
number
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index 901e7035bf8e..37230d3d94a0 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -563,32 +563,32 @@ struct wm_table lpddr4_wm_table = { .wm_inst = WM_A, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.65333, - .sr_exit_time_us = 12.5, - .sr_enter_plus_exit_time_us = 17.0, + .sr_exit_time_us = 5.32, + .sr_enter_plus_exit_time_us = 6.38, .valid = true, }, { .wm_inst = WM_B, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.65333, - .sr_exit_time_us = 12.5, - .sr_enter_plus_exit_time_us = 17.0, + .sr_exit_time_us = 9.82, + .sr_enter_plus_exit_time_us = 11.196, .valid = true, }, { .wm_inst = WM_C, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.65333, - .sr_exit_time_us = 12.5, - .sr_enter_plus_exit_time_us = 17.0, + .sr_exit_time_us = 9.89, + .sr_enter_plus_exit_time_us = 11.24, .valid = true, }, { .wm_inst = WM_D, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.65333, - .sr_exit_time_us = 12.5, - .sr_enter_plus_exit_time_us = 17.0, + .sr_exit_time_us = 9.748, + .sr_enter_plus_exit_time_us = 11.102, .valid = true, }, } |