diff options
| author | Will Deacon <will.deacon@arm.com> | 2016-02-18 15:05:57 +0300 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2016-02-18 18:02:44 +0300 |
| commit | cbf8277ef4562075eb4e3932ccd60cc11ee9454c (patch) | |
| tree | 87ad12c98e3264e58b7ad62c972ed8a5e8e1c068 | |
| parent | bc7f2ce0a7b54ba7703f81995fe434f0926424d2 (diff) | |
| download | linux-cbf8277ef4562075eb4e3932ccd60cc11ee9454c.tar.xz | |
iommu/arm-smmu: Treat IOMMU_DOMAIN_DMA as bypass for now
Until all upstream devices have their DMA ops swizzled to point at the
SMMU, we need to treat the IOMMU_DOMAIN_DMA domain as bypass to avoid
putting devices into an empty address space when detaching from VFIO.
Signed-off-by: Will Deacon <will.deacon@arm.com>
| -rw-r--r-- | drivers/iommu/arm-smmu-v3.c | 7 | ||||
| -rw-r--r-- | drivers/iommu/arm-smmu.c | 7 |
2 files changed, 13 insertions, 1 deletions
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index d96d45ddf500..4ff73ff64e49 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -1687,7 +1687,12 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) goto out_unlock; smmu_group->domain = smmu_domain; - smmu_group->ste.bypass = false; + + /* + * FIXME: This should always be "false" once we have IOMMU-backed + * DMA ops for all devices behind the SMMU. + */ + smmu_group->ste.bypass = domain->type == IOMMU_DOMAIN_DMA; ret = arm_smmu_install_ste_for_group(smmu_group); if (IS_ERR_VALUE(ret)) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index f21332a15040..2409e3bd3df2 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1094,6 +1094,13 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, if (ret) return ret == -EEXIST ? 0 : ret; + /* + * FIXME: This won't be needed once we have IOMMU-backed DMA ops + * for all devices behind the SMMU. + */ + if (smmu_domain->domain.type == IOMMU_DOMAIN_DMA) + return 0; + for (i = 0; i < cfg->num_streamids; ++i) { u32 idx, s2cr; |