ALSA: hda/realtek - Restore default value for ALC282

Restore the registers to prevent the abnormal digital power supply
rising ratio/sequence to the codec and causing the incorrect default
codec register restoration during initialization.

Signed-off-by: Kailang Yang <kailang@realtek.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>

1 files changed, 77 insertions, 0 deletions

diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 054489757528..189b1af7375d 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -2786,6 +2786,81 @@ static void alc269_shutup(struct hda_codec *codec)
 	snd_hda_shutup_pins(codec);
 }
 
+static void alc282_restore_default_value(struct hda_codec *codec)
+{
+	int val;
+
+	/* Power Down Control */
+	alc_write_coef_idx(codec, 0x03, 0x0002);
+	/* FIFO and filter clock */
+	alc_write_coef_idx(codec, 0x05, 0x0700);
+	/* DMIC control */
+	alc_write_coef_idx(codec, 0x07, 0x0200);
+	/* Analog clock */
+	val = alc_read_coef_idx(codec, 0x06);
+	alc_write_coef_idx(codec, 0x06, (val & ~0x00f0) | 0x0);
+	/* JD */
+	val = alc_read_coef_idx(codec, 0x08);
+	alc_write_coef_idx(codec, 0x08, (val & ~0xfffc) | 0x0c2c);
+	/* JD offset1 */
+	alc_write_coef_idx(codec, 0x0a, 0xcccc);
+	/* JD offset2 */
+	alc_write_coef_idx(codec, 0x0b, 0xcccc);
+	/* LDO1/2/3, DAC/ADC */
+	alc_write_coef_idx(codec, 0x0e, 0x6e00);
+	/* JD */
+	val = alc_read_coef_idx(codec, 0x0f);
+	alc_write_coef_idx(codec, 0x0f, (val & ~0xf800) | 0x1000);
+	/* Capless */
+	val = alc_read_coef_idx(codec, 0x10);
+	alc_write_coef_idx(codec, 0x10, (val & ~0xfc00) | 0x0c00);
+	/* Class D test 4 */
+	alc_write_coef_idx(codec, 0x6f, 0x0);
+	/* IO power down directly */
+	val = alc_read_coef_idx(codec, 0x0c);
+	alc_write_coef_idx(codec, 0x0c, (val & ~0xfe00) | 0x0);
+	/* ANC */
+	alc_write_coef_idx(codec, 0x34, 0xa0c0);
+	/* AGC MUX */
+	val = alc_read_coef_idx(codec, 0x16);
+	alc_write_coef_idx(codec, 0x16, (val & ~0x0008) | 0x0);
+	/* DAC simple content protection */
+	val = alc_read_coef_idx(codec, 0x1d);
+	alc_write_coef_idx(codec, 0x1d, (val & ~0x00e0) | 0x0);
+	/* ADC simple content protection */
+	val = alc_read_coef_idx(codec, 0x1f);
+	alc_write_coef_idx(codec, 0x1f, (val & ~0x00e0) | 0x0);
+	/* DAC ADC Zero Detection */
+	alc_write_coef_idx(codec, 0x21, 0x8804);
+	/* PLL */
+	alc_write_coef_idx(codec, 0x63, 0x2902);
+	/* capless control 2 */
+	alc_write_coef_idx(codec, 0x68, 0xa080);
+	/* capless control 3 */
+	alc_write_coef_idx(codec, 0x69, 0x3400);
+	/* capless control 4 */
+	alc_write_coef_idx(codec, 0x6a, 0x2f3e);
+	/* capless control 5 */
+	alc_write_coef_idx(codec, 0x6b, 0x0);
+	/* class D test 2 */
+	val = alc_read_coef_idx(codec, 0x6d);
+	alc_write_coef_idx(codec, 0x6d, (val & ~0x0fff) | 0x0900);
+	/* class D test 3 */
+	alc_write_coef_idx(codec, 0x6e, 0x110a);
+	/* class D test 5 */
+	val = alc_read_coef_idx(codec, 0x70);
+	alc_write_coef_idx(codec, 0x70, (val & ~0x00f8) | 0x00d8);
+	/* class D test 6 */
+	alc_write_coef_idx(codec, 0x71, 0x0014);
+	/* classD OCP */
+	alc_write_coef_idx(codec, 0x72, 0xc2ba);
+	/* classD pure DC test */
+	val = alc_read_coef_idx(codec, 0x77);
+	alc_write_coef_idx(codec, 0x77, (val & ~0x0f80) | 0x0);
+	/* Class D amp control */
+	alc_write_coef_idx(codec, 0x6c, 0xfc06);
+}
+
 static void alc282_init(struct hda_codec *codec)
 {
 	struct alc_spec *spec = codec->spec;
@@ -2793,6 +2868,8 @@ static void alc282_init(struct hda_codec *codec)
 	bool hp_pin_sense;
 	int coef78;
 
+	alc282_restore_default_value(codec);
+
 	if (!hp_pin)
 		return;
 	hp_pin_sense = snd_hda_jack_detect(codec, hp_pin);