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authorArnd Bergmann <arnd@arndb.de>2015-02-18 14:21:54 +0300
committerArnd Bergmann <arnd@arndb.de>2015-02-18 14:21:54 +0300
commitf495fe8998b31d113d6041c105fd5652ec2cf5ee (patch)
tree37bc5a51e7c769839a87e632af8b9b5e496de22f
parentd1bef995f61a6505a2ac69257b44fb9c59715953 (diff)
parentb51c05a331ff46d2b29e4007df938ec2dbbadfde (diff)
downloadlinux-f495fe8998b31d113d6041c105fd5652ec2cf5ee.tar.xz
Merge tag 'arm-soc/for-3.20/dts' of http://github.com/broadcom/stblinux into fixes
This pull request contains the following Broadcom SoCs Device Tree changes: - Ray adds support for the Cygnus i2c Device Tree controller on Cygnus SoCs - Fixes to the BCM63138 dtsi file for the L2 cache controller properties * tag 'arm-soc/for-3.20/dts' of http://github.com/broadcom/stblinux: ARM: dts: add I2C device nodes for Broadcom Cygnus ARM: dts: BCM63xx: fix L2 cache properties
-rw-r--r--arch/arm/boot/dts/bcm-cygnus.dtsi20
-rw-r--r--arch/arm/boot/dts/bcm63138.dtsi5
2 files changed, 23 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 5126f9e77a98..ff5fb6ab0b97 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -70,6 +70,26 @@
};
};
+ i2c0: i2c@18008000 {
+ compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
+ reg = <0x18008000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@1800b000 {
+ compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
+ reg = <0x1800b000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
uart0: serial@18020000 {
compatible = "snps,dw-apb-uart";
reg = <0x18020000 0x100>;
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index d2d8e94e0aa2..f46329c8ad75 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -66,8 +66,9 @@
reg = <0x1d000 0x1000>;
cache-unified;
cache-level = <2>;
- cache-sets = <16>;
- cache-size = <0x80000>;
+ cache-size = <524288>;
+ cache-sets = <1024>;
+ cache-line-size = <32>;
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
};