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| author | Sricharan R <r.sricharan@ti.com> | 2013-11-08 14:38:48 +0400 |
|---|---|---|
| committer | Rob Herring <rob.herring@calxeda.com> | 2013-12-03 09:35:23 +0400 |
| commit | f1e8e3811486b858bcc7190477bc6e4ea8f3488c (patch) | |
| tree | d2f066498ecfb277486c810e752ab133baa41c99 | |
| parent | f04bda90392b729fea9b0420b2a87aa6f2abfcd9 (diff) | |
| download | linux-f1e8e3811486b858bcc7190477bc6e4ea8f3488c.tar.xz | |
ARM: dts: doc: Document missing binding for omap5-mpu
The binding and support for omap5-mpu which has a cortex-a15
smp core, gic and integrated L2 cache has been existing for sometime.
So Documenting the missing binding here.
Cc: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| -rw-r--r-- | Documentation/devicetree/bindings/arm/omap/mpu.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt index 1a5a42ce21bb..83f405bde138 100644 --- a/Documentation/devicetree/bindings/arm/omap/mpu.txt +++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt @@ -7,10 +7,18 @@ The MPU contain CPUs, GIC, L2 cache and a local PRCM. Required properties: - compatible : Should be "ti,omap3-mpu" for OMAP3 Should be "ti,omap4-mpu" for OMAP4 + Should be "ti,omap5-mpu" for OMAP5 - ti,hwmods: "mpu" Examples: +- For an OMAP5 SMP system: + +mpu { + compatible = "ti,omap5-mpu"; + ti,hwmods = "mpu" +}; + - For an OMAP4 SMP system: mpu { |