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authorSam Protsenko <semen.protsenko@linaro.org>2024-06-21 02:13:37 +0300
committerHerbert Xu <herbert@gondor.apana.org.au>2024-06-28 04:35:48 +0300
commite003d67067043488595f33f3a82230a4281686ca (patch)
treed038234727fab103cfd2146e3df3c8ce10d0479c
parent81da8056e92bd255178413d36382653ed5a1a230 (diff)
downloadlinux-e003d67067043488595f33f3a82230a4281686ca.tar.xz
hwrng: exynos - Implement bus clock control
Some SoCs like Exynos850 might require the SSS bus clock (PCLK) to be enabled in order to access TRNG registers. Add and handle the optional PCLK clock accordingly to make it possible. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
-rw-r--r--drivers/char/hw_random/exynos-trng.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/char/hw_random/exynos-trng.c b/drivers/char/hw_random/exynos-trng.c
index 997bd22f4498..6ef2ee6c9804 100644
--- a/drivers/char/hw_random/exynos-trng.c
+++ b/drivers/char/hw_random/exynos-trng.c
@@ -47,7 +47,8 @@
struct exynos_trng_dev {
struct device *dev;
void __iomem *mem;
- struct clk *clk;
+ struct clk *clk; /* operating clock */
+ struct clk *pclk; /* bus clock */
struct hwrng rng;
};
@@ -141,6 +142,13 @@ static int exynos_trng_probe(struct platform_device *pdev)
goto err_clock;
}
+ trng->pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk");
+ if (IS_ERR(trng->pclk)) {
+ ret = dev_err_probe(&pdev->dev, PTR_ERR(trng->pclk),
+ "Could not get pclk\n");
+ goto err_clock;
+ }
+
ret = devm_hwrng_register(&pdev->dev, &trng->rng);
if (ret) {
dev_err(&pdev->dev, "Could not register hwrng device.\n");