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| author | Christoph Hellwig <hch@lst.de> | 2019-08-26 10:22:13 +0300 |
|---|---|---|
| committer | Christoph Hellwig <hch@lst.de> | 2019-08-29 17:43:41 +0300 |
| commit | db91427b6502e8e46db4b616e4eaa9b9cf4e6363 (patch) | |
| tree | e7db7c193c9f0ad6561dbbd8c4512592f28825b2 | |
| parent | 3e4e1d3fb89193cc072858e1469d6f2926c603f7 (diff) | |
| download | linux-db91427b6502e8e46db4b616e4eaa9b9cf4e6363.tar.xz | |
MIPS: document mixing "slightly different CCAs"
Based on an email from Paul Burton, quoting section 4.8 "Cacheability and
Coherency Attributes and Access Types" of "MIPS Architecture Volume 1:
Introduction to the MIPS32 Architecture" (MD00080, revision 6.01).
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Paul Burton <paul.burton@mips.com>
| -rw-r--r-- | arch/mips/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index fc88f68ea1ee..aff1cadeea43 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1119,6 +1119,13 @@ config DMA_PERDEV_COHERENT config DMA_NONCOHERENT bool + # + # MIPS allows mixing "slightly different" Cacheability and Coherency + # Attribute bits. It is believed that the uncached access through + # KSEG1 and the implementation specific "uncached accelerated" used + # by pgprot_writcombine can be mixed, and the latter sometimes provides + # significant advantages. + # select ARCH_HAS_DMA_WRITE_COMBINE select ARCH_HAS_SYNC_DMA_FOR_DEVICE select ARCH_HAS_UNCACHED_SEGMENT |