diff options
| author | Stephen Boyd <sboyd@kernel.org> | 2024-02-28 01:16:38 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-02-28 01:16:38 +0300 |
| commit | d289ca74e96afad6d1815d9218d40e867feeef3d (patch) | |
| tree | 3fa19c6b8546fba642d74a122adb67233116f0f8 | |
| parent | 6613476e225e090cc9aad49be7fa504e290dd33d (diff) | |
| parent | 61f4399c74d0677ee64e42f7b8d4ab01ee39de45 (diff) | |
| download | linux-d289ca74e96afad6d1815d9218d40e867feeef3d.tar.xz | |
Merge tag 'samsung-clk-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clock driver updates from Krzysztof Kozlowski:
Google GS101:
- Register the CMU MISC clock controller earlier, so the Multi Core
Timer clocksource can use it
- Add PERIC0 and PERIC1 clock controllers
Exynos850:
- Add PDMA clocks
- Add CPU cluster 0 and 1 (CMU_CPUCLK0/CMU_CPUCLK1) clock controllers
- Propagate SPI IPCLK rate change to parents, so the SPI will get
proper clock rates
- Refactor the generic Samsung CPU clock controllers code, preparing it
for supporting Exynos850 CPU clocks
* tag 'samsung-clk-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (25 commits)
clk: samsung: Add CPU clock support for Exynos850
clk: samsung: Pass mask to wait_until_mux_stable()
clk: samsung: Keep register offsets in chip specific structure
clk: samsung: Keep CPU clock chip specific data in a dedicated struct
clk: samsung: Pass register layout type explicitly to CLK_CPU()
clk: samsung: Pass actual CPU clock registers base to CPU_CLK()
clk: samsung: Group CPU clock functions by chip
clk: samsung: Use single CPU clock notifier callback for all chips
clk: samsung: Reduce params count in exynos_register_cpu_clock()
clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c
clk: samsung: Improve clk-cpu.c style
dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1
clk: samsung: gs101: add support for cmu_peric1
clk: samsung: gs101: drop extra empty line
dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
clk: samsung: exynos850: Propagate SPI IPCLK rate change
clk: samsung: gs101: gpio_peric0_pclk needs to be kept on
clk: samsung: exynos850: Add PDMA clocks
dt-bindings: clock: tesla,fsd: Fix spelling mistake
clk: samsung: gs101: add support for cmu_peric0
...
| -rw-r--r-- | Documentation/devicetree/bindings/clock/google,gs101-clock.yaml | 32 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml | 42 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml | 2 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-cpu.c | 556 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-cpu.h | 53 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos3250.c | 2 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 9 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5250.c | 5 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 16 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 10 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos850.c | 43 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-gs101.c | 942 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk.h | 5 | ||||
| -rw-r--r-- | include/dt-bindings/clock/exynos850.h | 56 | ||||
| -rw-r--r-- | include/dt-bindings/clock/google,gs101.h | 129 |
15 files changed, 1660 insertions, 242 deletions
diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 3eebc03a309b..1d2bcea41c85 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -30,14 +30,16 @@ properties: - google,gs101-cmu-top - google,gs101-cmu-apm - google,gs101-cmu-misc + - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 clocks: minItems: 1 - maxItems: 2 + maxItems: 3 clock-names: minItems: 1 - maxItems: 2 + maxItems: 3 "#clock-cells": const: 1 @@ -85,8 +87,30 @@ allOf: clock-names: items: - - const: dout_cmu_misc_bus - - const: dout_cmu_misc_sss + - const: bus + - const: sss + + - if: + properties: + compatible: + contains: + enum: + - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP) + - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: ip additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml index c752c8985a53..cdc5ded59fe5 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -36,6 +36,8 @@ properties: - samsung,exynos850-cmu-aud - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core + - samsung,exynos850-cmu-cpucl0 + - samsung,exynos850-cmu-cpucl1 - samsung,exynos850-cmu-dpu - samsung,exynos850-cmu-g3d - samsung,exynos850-cmu-hsi @@ -156,6 +158,46 @@ allOf: properties: compatible: contains: + const: samsung,exynos850-cmu-cpucl0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CPUCL0 switch clock (from CMU_TOP) + - description: CPUCL0 debug clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cpucl0_switch + - const: dout_cpucl0_dbg + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-cpucl1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CPUCL1 switch clock (from CMU_TOP) + - description: CPUCL1 debug clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cpucl1_switch + - const: dout_cpucl1_dbg + + - if: + properties: + compatible: + contains: const: samsung,exynos850-cmu-dpu then: diff --git a/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml index dc808e2f8327..b370a10a23a6 100644 --- a/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml +++ b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml @@ -12,7 +12,7 @@ maintainers: description: | FSD clock controller consist of several clock management unit - (CMU), which generates clocks for various inteernal SoC blocks. + (CMU), which generates clocks for various internal SoC blocks. The root clock comes from external OSC clock (24 MHz). All available clocks are defined as preprocessor macros in diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 3e62ade120c5..fbf4c4208e06 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -16,51 +16,106 @@ * of the SoC or supplied after the SoC characterization. * * The below implementation of the CPU clock allows the rate changes of the CPU - * clock and the corresponding rate changes of the auxillary clocks of the CPU + * clock and the corresponding rate changes of the auxiliary clocks of the CPU * domain. The platform clock driver provides a clock register configuration * for each configurable rate which is then used to program the clock hardware - * registers to acheive a fast co-oridinated rate change for all the CPU domain + * registers to achieve a fast coordinated rate change for all the CPU domain * clocks. * * On a rate change request for the CPU clock, the rate change is propagated - * upto the PLL supplying the clock to the CPU domain clock blocks. While the + * up to the PLL supplying the clock to the CPU domain clock blocks. While the * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an * alternate clock source. If required, the alternate clock source is divided * down in order to keep the output clock rate within the previous OPP limits. -*/ + */ +#include <linux/delay.h> #include <linux/errno.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/clk.h> #include <linux/clk-provider.h> + +#include "clk.h" #include "clk-cpu.h" -#define E4210_SRC_CPU 0x0 -#define E4210_STAT_CPU 0x200 -#define E4210_DIV_CPU0 0x300 -#define E4210_DIV_CPU1 0x304 -#define E4210_DIV_STAT_CPU0 0x400 -#define E4210_DIV_STAT_CPU1 0x404 - -#define E5433_MUX_SEL2 0x008 -#define E5433_MUX_STAT2 0x208 -#define E5433_DIV_CPU0 0x400 -#define E5433_DIV_CPU1 0x404 -#define E5433_DIV_STAT_CPU0 0x500 -#define E5433_DIV_STAT_CPU1 0x504 - -#define E4210_DIV0_RATIO0_MASK 0x7 -#define E4210_DIV1_HPM_MASK (0x7 << 4) -#define E4210_DIV1_COPY_MASK (0x7 << 0) -#define E4210_MUX_HPM_MASK (1 << 20) -#define E4210_DIV0_ATB_SHIFT 16 -#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT) +struct exynos_cpuclk; + +typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata, + struct exynos_cpuclk *cpuclk); + +/** + * struct exynos_cpuclk_regs - Register offsets for CPU related clocks + * @mux_sel: offset of CPU MUX_SEL register (for selecting MUX clock parent) + * @mux_stat: offset of CPU MUX_STAT register (for checking MUX clock status) + * @div_cpu0: offset of CPU DIV0 register (for modifying divider values) + * @div_cpu1: offset of CPU DIV1 register (for modifying divider values) + * @div_stat_cpu0: offset of CPU DIV0_STAT register (for checking DIV status) + * @div_stat_cpu1: offset of CPU DIV1_STAT register (for checking DIV status) + * @mux: offset of MUX register for choosing CPU clock source + * @divs: offsets of DIV registers (ACLK, ATCLK, PCLKDBG and PERIPHCLK) + */ +struct exynos_cpuclk_regs { + u32 mux_sel; + u32 mux_stat; + u32 div_cpu0; + u32 div_cpu1; + u32 div_stat_cpu0; + u32 div_stat_cpu1; + + u32 mux; + u32 divs[4]; +}; + +/** + * struct exynos_cpuclk_chip - Chip specific data for CPU clock + * @regs: register offsets for CPU related clocks + * @pre_rate_cb: callback to run before CPU clock rate change + * @post_rate_cb: callback to run after CPU clock rate change + */ +struct exynos_cpuclk_chip { + const struct exynos_cpuclk_regs *regs; + exynos_rate_change_fn_t pre_rate_cb; + exynos_rate_change_fn_t post_rate_cb; +}; + +/** + * struct exynos_cpuclk - information about clock supplied to a CPU core + * @hw: handle between CCF and CPU clock + * @alt_parent: alternate parent clock to use when switching the speed + * of the primary parent clock + * @base: start address of the CPU clock registers block + * @lock: cpu clock domain register access lock + * @cfg: cpu clock rate configuration data + * @num_cfgs: number of array elements in @cfg array + * @clk_nb: clock notifier registered for changes in clock speed of the + * primary parent clock + * @flags: configuration flags for the CPU clock + * @chip: chip-specific data for the CPU clock + * + * This structure holds information required for programming the CPU clock for + * various clock speeds. + */ +struct exynos_cpuclk { + struct clk_hw hw; + const struct clk_hw *alt_parent; + void __iomem *base; + spinlock_t *lock; + const struct exynos_cpuclk_cfg_data *cfg; + const unsigned long num_cfgs; + struct notifier_block clk_nb; + unsigned long flags; + const struct exynos_cpuclk_chip *chip; +}; +/* ---- Common code --------------------------------------------------------- */ + +/* Divider stabilization time, msec */ +#define MAX_STAB_TIME 10 #define MAX_DIV 8 -#define DIV_MASK 7 -#define DIV_MASK_ALL 0xffffffff -#define MUX_MASK 7 +#define DIV_MASK GENMASK(2, 0) +#define DIV_MASK_ALL GENMASK(31, 0) +#define MUX_MASK GENMASK(2, 0) /* * Helper function to wait until divider(s) have stabilized after the divider @@ -68,7 +123,7 @@ */ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) { - unsigned long timeout = jiffies + msecs_to_jiffies(10); + unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME); do { if (!(readl(div_reg) & mask)) @@ -86,72 +141,65 @@ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) * value was changed. */ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, - unsigned long mux_value) + unsigned long mask, unsigned long mux_value) { - unsigned long timeout = jiffies + msecs_to_jiffies(10); + unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME); do { - if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) + if (((readl(mux_reg) >> mux_pos) & mask) == mux_value) return; } while (time_before(jiffies, timeout)); - if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) + if (((readl(mux_reg) >> mux_pos) & mask) == mux_value) return; pr_err("%s: re-parenting mux timed-out\n", __func__); } -/* common round rate callback useable for all types of CPU clocks */ -static long exynos_cpuclk_round_rate(struct clk_hw *hw, - unsigned long drate, unsigned long *prate) -{ - struct clk_hw *parent = clk_hw_get_parent(hw); - *prate = clk_hw_round_rate(parent, drate); - return *prate; -} - -/* common recalc rate callback useable for all types of CPU clocks */ -static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - /* - * The CPU clock output (armclk) rate is the same as its parent - * rate. Although there exist certain dividers inside the CPU - * clock block that could be used to divide the parent clock, - * the driver does not make use of them currently, except during - * frequency transitions. - */ - return parent_rate; -} - -static const struct clk_ops exynos_cpuclk_clk_ops = { - .recalc_rate = exynos_cpuclk_recalc_rate, - .round_rate = exynos_cpuclk_round_rate, -}; - /* * Helper function to set the 'safe' dividers for the CPU clock. The parameters * div and mask contain the divider value and the register bit mask of the * dividers to be programmed. */ -static void exynos_set_safe_div(void __iomem *base, unsigned long div, - unsigned long mask) +static void exynos_set_safe_div(struct exynos_cpuclk *cpuclk, unsigned long div, + unsigned long mask) { + const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs; + void __iomem *base = cpuclk->base; unsigned long div0; - div0 = readl(base + E4210_DIV_CPU0); + div0 = readl(base + regs->div_cpu0); div0 = (div0 & ~mask) | (div & mask); - writel(div0, base + E4210_DIV_CPU0); - wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask); + writel(div0, base + regs->div_cpu0); + wait_until_divider_stable(base + regs->div_stat_cpu0, mask); } +/* ---- Exynos 3/4/5 -------------------------------------------------------- */ + +#define E4210_DIV0_RATIO0_MASK GENMASK(2, 0) +#define E4210_DIV1_HPM_MASK GENMASK(6, 4) +#define E4210_DIV1_COPY_MASK GENMASK(2, 0) +#define E4210_MUX_HPM_MASK BIT(20) +#define E4210_DIV0_ATB_SHIFT 16 +#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT) + +static const struct exynos_cpuclk_regs e4210_cpuclk_regs = { + .mux_sel = 0x200, + .mux_stat = 0x400, + .div_cpu0 = 0x500, + .div_cpu1 = 0x504, + .div_stat_cpu0 = 0x600, + .div_stat_cpu1 = 0x604, +}; + /* handler for pre-rate change notification from parent clock */ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, - struct exynos_cpuclk *cpuclk, void __iomem *base) + struct exynos_cpuclk *cpuclk) { const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; + const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs; + void __iomem *base = cpuclk->base; unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); - unsigned long alt_div = 0, alt_div_mask = DIV_MASK; unsigned long div0, div1 = 0, mux_reg; unsigned long flags; @@ -172,8 +220,8 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, div0 = cfg_data->div0; if (cpuclk->flags & CLK_CPU_HAS_DIV1) { div1 = cfg_data->div1; - if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK) - div1 = readl(base + E4210_DIV_CPU1) & + if (readl(base + regs->mux_sel) & E4210_MUX_HPM_MASK) + div1 = readl(base + regs->div_cpu1) & (E4210_DIV1_HPM_MASK | E4210_DIV1_COPY_MASK); } @@ -187,6 +235,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, */ if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) { unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate); + unsigned long alt_div, alt_div_mask = DIV_MASK; alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1; WARN_ON(alt_div >= MAX_DIV); @@ -199,23 +248,23 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, alt_div |= E4210_DIV0_ATB_MASK; alt_div_mask |= E4210_DIV0_ATB_MASK; } - exynos_set_safe_div(base, alt_div, alt_div_mask); + exynos_set_safe_div(cpuclk, alt_div, alt_div_mask); div0 |= alt_div; } /* select sclk_mpll as the alternate parent */ - mux_reg = readl(base + E4210_SRC_CPU); - writel(mux_reg | (1 << 16), base + E4210_SRC_CPU); - wait_until_mux_stable(base + E4210_STAT_CPU, 16, 2); + mux_reg = readl(base + regs->mux_sel); + writel(mux_reg | (1 << 16), base + regs->mux_sel); + wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 2); /* alternate parent is active now. set the dividers */ - writel(div0, base + E4210_DIV_CPU0); - wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL); + writel(div0, base + regs->div_cpu0); + wait_until_divider_stable(base + regs->div_stat_cpu0, DIV_MASK_ALL); if (cpuclk->flags & CLK_CPU_HAS_DIV1) { - writel(div1, base + E4210_DIV_CPU1); - wait_until_divider_stable(base + E4210_DIV_STAT_CPU1, - DIV_MASK_ALL); + writel(div1, base + regs->div_cpu1); + wait_until_divider_stable(base + regs->div_stat_cpu1, + DIV_MASK_ALL); } spin_unlock_irqrestore(cpuclk->lock, flags); @@ -224,9 +273,11 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, /* handler for post-rate change notification from parent clock */ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, - struct exynos_cpuclk *cpuclk, void __iomem *base) + struct exynos_cpuclk *cpuclk) { const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; + const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs; + void __iomem *base = cpuclk->base; unsigned long div = 0, div_mask = DIV_MASK; unsigned long mux_reg; unsigned long flags; @@ -243,43 +294,39 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, spin_lock_irqsave(cpuclk->lock, flags); /* select mout_apll as the alternate parent */ - mux_reg = readl(base + E4210_SRC_CPU); - writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU); - wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1); + mux_reg = readl(base + regs->mux_sel); + writel(mux_reg & ~(1 << 16), base + regs->mux_sel); + wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 1); if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK); div_mask |= E4210_DIV0_ATB_MASK; } - exynos_set_safe_div(base, div, div_mask); + exynos_set_safe_div(cpuclk, div, div_mask); spin_unlock_irqrestore(cpuclk->lock, flags); return 0; } -/* - * Helper function to set the 'safe' dividers for the CPU clock. The parameters - * div and mask contain the divider value and the register bit mask of the - * dividers to be programmed. - */ -static void exynos5433_set_safe_div(void __iomem *base, unsigned long div, - unsigned long mask) -{ - unsigned long div0; +/* ---- Exynos5433 ---------------------------------------------------------- */ - div0 = readl(base + E5433_DIV_CPU0); - div0 = (div0 & ~mask) | (div & mask); - writel(div0, base + E5433_DIV_CPU0); - wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask); -} +static const struct exynos_cpuclk_regs e5433_cpuclk_regs = { + .mux_sel = 0x208, + .mux_stat = 0x408, + .div_cpu0 = 0x600, + .div_cpu1 = 0x604, + .div_stat_cpu0 = 0x700, + .div_stat_cpu1 = 0x704, +}; /* handler for pre-rate change notification from parent clock */ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, - struct exynos_cpuclk *cpuclk, void __iomem *base) + struct exynos_cpuclk *cpuclk) { const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; + const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs; + void __iomem *base = cpuclk->base; unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); - unsigned long alt_div = 0, alt_div_mask = DIV_MASK; unsigned long div0, div1 = 0, mux_reg; unsigned long flags; @@ -309,25 +356,26 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, */ if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) { unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate); + unsigned long alt_div, alt_div_mask = DIV_MASK; alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1; WARN_ON(alt_div >= MAX_DIV); - exynos5433_set_safe_div(base, alt_div, alt_div_mask); + exynos_set_safe_div(cpuclk, alt_div, alt_div_mask); div0 |= alt_div; } /* select the alternate parent */ - mux_reg = readl(base + E5433_MUX_SEL2); - writel(mux_reg | 1, base + E5433_MUX_SEL2); - wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2); + mux_reg = readl(base + regs->mux_sel); + writel(mux_reg | 1, base + regs->mux_sel); + wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 2); /* alternate parent is active now. set the dividers */ - writel(div0, base + E5433_DIV_CPU0); - wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, DIV_MASK_ALL); + writel(div0, base + regs->div_cpu0); + wait_until_divider_stable(base + regs->div_stat_cpu0, DIV_MASK_ALL); - writel(div1, base + E5433_DIV_CPU1); - wait_until_divider_stable(base + E5433_DIV_STAT_CPU1, DIV_MASK_ALL); + writel(div1, base + regs->div_cpu1); + wait_until_divider_stable(base + regs->div_stat_cpu1, DIV_MASK_ALL); spin_unlock_irqrestore(cpuclk->lock, flags); return 0; @@ -335,8 +383,10 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, /* handler for post-rate change notification from parent clock */ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata, - struct exynos_cpuclk *cpuclk, void __iomem *base) + struct exynos_cpuclk *cpuclk) { + const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs; + void __iomem *base = cpuclk->base; unsigned long div = 0, div_mask = DIV_MASK; unsigned long mux_reg; unsigned long flags; @@ -344,73 +394,265 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata, spin_lock_irqsave(cpuclk->lock, flags); /* select apll as the alternate parent */ - mux_reg = readl(base + E5433_MUX_SEL2); - writel(mux_reg & ~1, base + E5433_MUX_SEL2); - wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1); + mux_reg = readl(base + regs->mux_sel); + writel(mux_reg & ~1, base + regs->mux_sel); + wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 1); - exynos5433_set_safe_div(base, div, div_mask); + exynos_set_safe_div(cpuclk, div, div_mask); spin_unlock_irqrestore(cpuclk->lock, flags); return 0; } +/* ---- Exynos850 ----------------------------------------------------------- */ + +#define E850_DIV_RATIO_MASK GENMASK(3, 0) +#define E850_BUSY_MASK BIT(16) + +/* Max time for divider or mux to stabilize, usec */ +#define E850_DIV_MUX_STAB_TIME 100 +/* OSCCLK clock rate, Hz */ +#define E850_OSCCLK (26 * MHZ) + +static const struct exynos_cpuclk_regs e850cl0_cpuclk_regs = { + .mux = 0x100c, + .divs = { 0x1800, 0x1808, 0x180c, 0x1810 }, +}; + +static const struct exynos_cpuclk_regs e850cl1_cpuclk_regs = { + .mux = 0x1000, + .divs = { 0x1800, 0x1808, 0x180c, 0x1810 }, +}; + /* - * This notifier function is called for the pre-rate and post-rate change - * notifications of the parent clock of cpuclk. + * Set alternate parent rate to "rate" value or less. + * + * rate: Desired alt_parent rate, or 0 for max alt_parent rate + * + * Exynos850 doesn't have CPU clock divider in CMU_CPUCLx block (CMUREF divider + * doesn't affect CPU speed). So CPUCLx_SWITCH divider from CMU_TOP is used + * instead to adjust alternate parent speed. + * + * It's possible to use clk_set_max_rate() instead of this function, but it + * would set overly pessimistic rate values to alternate parent. */ -static int exynos_cpuclk_notifier_cb(struct notifier_block *nb, - unsigned long event, void *data) +static int exynos850_alt_parent_set_max_rate(const struct clk_hw *alt_parent, + unsigned long rate) { - struct clk_notifier_data *ndata = data; - struct exynos_cpuclk *cpuclk; - void __iomem *base; - int err = 0; + struct clk_hw *clk_div, *clk_divp; + unsigned long divp_rate, div_rate, div; + int ret; + + /* Divider from CMU_TOP */ + clk_div = clk_hw_get_parent(alt_parent); + if (!clk_div) + return -ENOENT; + /* Divider's parent from CMU_TOP */ + clk_divp = clk_hw_get_parent(clk_div); + if (!clk_divp) + return -ENOENT; + /* Divider input rate */ + divp_rate = clk_hw_get_rate(clk_divp); + if (!divp_rate) + return -EINVAL; - cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb); - base = cpuclk->ctrl_base; + /* Calculate new alt_parent rate for integer divider value */ + if (rate == 0) + div = 1; + else + div = DIV_ROUND_UP(divp_rate, rate); + div_rate = DIV_ROUND_UP(divp_rate, div); + WARN_ON(div >= MAX_DIV); - if (event == PRE_RATE_CHANGE) - err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base); - else if (event == POST_RATE_CHANGE) - err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base); + /* alt_parent will propagate this change up to the divider */ + ret = clk_set_rate(alt_parent->clk, div_rate); + if (ret) + return ret; + udelay(E850_DIV_MUX_STAB_TIME); - return notifier_from_errno(err); + return 0; +} + +/* Handler for pre-rate change notification from parent clock */ +static int exynos850_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, + struct exynos_cpuclk *cpuclk) +{ + const unsigned int shifts[4] = { 16, 12, 8, 4 }; /* E850_CPU_DIV0() */ + const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs; + const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; + const struct clk_hw *alt_parent = cpuclk->alt_parent; + void __iomem *base = cpuclk->base; + unsigned long alt_prate = clk_hw_get_rate(alt_parent); + unsigned long flags; + u32 mux_reg; + size_t i; + int ret; + + /* No actions are needed when switching to or from OSCCLK parent */ + if (ndata->new_rate == E850_OSCCLK || ndata->old_rate == E850_OSCCLK) + return 0; + + /* Find out the divider values to use for clock data */ + while ((cfg_data->prate * 1000) != ndata->new_rate) { + if (cfg_data->prate == 0) + return -EINVAL; + cfg_data++; + } + + /* + * If the old parent clock speed is less than the clock speed of + * the alternate parent, then it should be ensured that at no point + * the armclk speed is more than the old_prate until the dividers are + * set. Also workaround the issue of the dividers being set to lower + * values before the parent clock speed is set to new lower speed + * (this can result in too high speed of armclk output clocks). + */ + if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) { + unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate); + + ret = exynos850_alt_parent_set_max_rate(alt_parent, tmp_rate); + if (ret) + return ret; + } + + spin_lock_irqsave(cpuclk->lock, flags); + + /* Select the alternate parent */ + mux_reg = readl(base + regs->mux); + writel(mux_reg | 1, base + regs->mux); + wait_until_mux_stable(base + regs->mux, 16, 1, 0); + + /* Alternate parent is active now. Set the dividers */ + for (i = 0; i < ARRAY_SIZE(shifts); ++i) { + unsigned long div = (cfg_data->div0 >> shifts[i]) & 0xf; + u32 val; + + val = readl(base + regs->divs[i]); + val = (val & ~E850_DIV_RATIO_MASK) | div; + writel(val, base + regs->divs[i]); + wait_until_divider_stable(base + regs->divs[i], E850_BUSY_MASK); + } + + spin_unlock_irqrestore(cpuclk->lock, flags); + + return 0; +} + +/* Handler for post-rate change notification from parent clock */ +static int exynos850_cpuclk_post_rate_change(struct clk_notifier_data *ndata, + struct exynos_cpuclk *cpuclk) +{ + const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs; + const struct clk_hw *alt_parent = cpuclk->alt_parent; + void __iomem *base = cpuclk->base; + unsigned long flags; + u32 mux_reg; + + /* No actions are needed when switching to or from OSCCLK parent */ + if (ndata->new_rate == E850_OSCCLK || ndata->old_rate == E850_OSCCLK) + return 0; + + spin_lock_irqsave(cpuclk->lock, flags); + + /* Select main parent (PLL) for mux */ + mux_reg = readl(base + regs->mux); + writel(mux_reg & ~1, base + regs->mux); + wait_until_mux_stable(base + regs->mux, 16, 1, 0); + + spin_unlock_irqrestore(cpuclk->lock, flags); + + /* Set alt_parent rate back to max */ + return exynos850_alt_parent_set_max_rate(alt_parent, 0); +} + +/* -------------------------------------------------------------------------- */ + +/* Common round rate callback usable for all types of CPU clocks */ +static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate, + unsigned long *prate) +{ + struct clk_hw *parent = clk_hw_get_parent(hw); + *prate = clk_hw_round_rate(parent, drate); + return *prate; } +/* Common recalc rate callback usable for all types of CPU clocks */ +static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* + * The CPU clock output (armclk) rate is the same as its parent + * rate. Although there exist certain dividers inside the CPU + * clock block that could be used to divide the parent clock, + * the driver does not make use of them currently, except during + * frequency transitions. + */ + return parent_rate; +} + +static const struct clk_ops exynos_cpuclk_clk_ops = { + .recalc_rate = exynos_cpuclk_recalc_rate, + .round_rate = exynos_cpuclk_round_rate, +}; + /* * This notifier function is called for the pre-rate and post-rate change * notifications of the parent clock of cpuclk. */ -static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb, - unsigned long event, void *data) +static int exynos_cpuclk_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) { struct clk_notifier_data *ndata = data; struct exynos_cpuclk *cpuclk; - void __iomem *base; int err = 0; cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb); - base = cpuclk->ctrl_base; if (event == PRE_RATE_CHANGE) - err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base); + err = cpuclk->chip->pre_rate_cb(ndata, cpuclk); else if (event == POST_RATE_CHANGE) - err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base); + err = cpuclk->chip->post_rate_cb(ndata, cpuclk); return notifier_from_errno(err); } +static const struct exynos_cpuclk_chip exynos_clkcpu_chips[] = { + [CPUCLK_LAYOUT_E4210] = { + .regs = &e4210_cpuclk_regs, + .pre_rate_cb = exynos_cpuclk_pre_rate_change, + .post_rate_cb = exynos_cpuclk_post_rate_change, + }, + [CPUCLK_LAYOUT_E5433] = { + .regs = &e5433_cpuclk_regs, + .pre_rate_cb = exynos5433_cpuclk_pre_rate_change, + .post_rate_cb = exynos5433_cpuclk_post_rate_change, + }, + [CPUCLK_LAYOUT_E850_CL0] = { + .regs = &e850cl0_cpuclk_regs, + .pre_rate_cb = exynos850_cpuclk_pre_rate_change, + .post_rate_cb = exynos850_cpuclk_post_rate_change, + }, + [CPUCLK_LAYOUT_E850_CL1] = { + .regs = &e850cl1_cpuclk_regs, + .pre_rate_cb = exynos850_cpuclk_pre_rate_change, + .post_rate_cb = exynos850_cpuclk_post_rate_change, + }, +}; + /* helper function to register a CPU clock */ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, - unsigned int lookup_id, const char *name, - const struct clk_hw *parent, const struct clk_hw *alt_parent, - unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg, - unsigned long num_cfgs, unsigned long flags) + const struct samsung_cpu_clock *clk_data) { + const struct clk_hw *parent, *alt_parent; + struct clk_hw **hws; struct exynos_cpuclk *cpuclk; struct clk_init_data init; const char *parent_name; + unsigned int num_cfgs; int ret = 0; + hws = ctx->clk_data.hws; + parent = hws[clk_data->parent_id]; + alt_parent = hws[clk_data->alt_parent_id]; if (IS_ERR(parent) || IS_ERR(alt_parent)) { pr_err("%s: invalid parent clock(s)\n", __func__); return -EINVAL; @@ -422,7 +664,7 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, parent_name = clk_hw_get_name(parent); - init.name = name; + init.name = clk_data->name; init.flags = CLK_SET_RATE_PARENT; init.parent_names = &parent_name; init.num_parents = 1; @@ -430,23 +672,25 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, cpuclk->alt_parent = alt_parent; cpuclk->hw.init = &init; - cpuclk->ctrl_base = ctx->reg_base + offset; + cpuclk->base = ctx->reg_base + clk_data->offset; cpuclk->lock = &ctx->lock; - cpuclk->flags = flags; - if (flags & CLK_CPU_HAS_E5433_REGS_LAYOUT) - cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb; - else - cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb; - + cpuclk->flags = clk_data->flags; + cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb; + cpuclk->chip = &exynos_clkcpu_chips[clk_data->reg_layout]; ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb); if (ret) { pr_err("%s: failed to register clock notifier for %s\n", - __func__, name); + __func__, clk_data->name); goto free_cpuclk; } - cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL); + /* Find count of configuration rates in cfg */ + for (num_cfgs = 0; clk_data->cfg[num_cfgs].prate != 0; ) + num_cfgs++; + + cpuclk->cfg = kmemdup(clk_data->cfg, sizeof(*clk_data->cfg) * num_cfgs, + GFP_KERNEL); if (!cpuclk->cfg) { ret = -ENOMEM; goto unregister_clk_nb; @@ -454,11 +698,12 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, ret = clk_hw_register(NULL, &cpuclk->hw); if (ret) { - pr_err("%s: could not register cpuclk %s\n", __func__, name); + pr_err("%s: could not register cpuclk %s\n", __func__, + clk_data->name); goto free_cpuclk_data; } - samsung_clk_add_lookup(ctx, &cpuclk->hw, lookup_id); + samsung_clk_add_lookup(ctx, &cpuclk->hw, clk_data->id); return 0; free_cpuclk_data: @@ -474,16 +719,7 @@ void __init samsung_clk_register_cpu(struct samsung_clk_provider *ctx, const struct samsung_cpu_clock *list, unsigned int nr_clk) { unsigned int idx; - unsigned int num_cfgs; - struct clk_hw **hws = ctx->clk_data.hws; - for (idx = 0; idx < nr_clk; idx++, list++) { - /* find count of configuration rates in cfg */ - for (num_cfgs = 0; list->cfg[num_cfgs].prate != 0; ) - num_cfgs++; - - exynos_register_cpu_clock(ctx, list->id, list->name, hws[list->parent_id], - hws[list->alt_parent_id], list->offset, list->cfg, num_cfgs, - list->flags); - } + for (idx = 0; idx < nr_clk; idx++) + exynos_register_cpu_clock(ctx, &list[idx]); } diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index 0164bd9ad021..892843611b0a 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -8,7 +8,24 @@ #ifndef __SAMSUNG_CLK_CPU_H #define __SAMSUNG_CLK_CPU_H -#include "clk.h" +/* The CPU clock registers have DIV1 configuration register */ +#define CLK_CPU_HAS_DIV1 BIT(0) +/* When ALT parent is active, debug clocks need safe divider values */ +#define CLK_CPU_NEEDS_DEBUG_ALT_DIV BIT(1) + +/** + * enum exynos_cpuclk_layout - CPU clock registers layout compatibility + * @CPUCLK_LAYOUT_E4210: Exynos4210 compatible layout + * @CPUCLK_LAYOUT_E5433: Exynos5433 compatible layout + * @CPUCLK_LAYOUT_E850_CL0: Exynos850 cluster 0 compatible layout + * @CPUCLK_LAYOUT_E850_CL1: Exynos850 cluster 1 compatible layout + */ +enum exynos_cpuclk_layout { + CPUCLK_LAYOUT_E4210, + CPUCLK_LAYOUT_E5433, + CPUCLK_LAYOUT_E850_CL0, + CPUCLK_LAYOUT_E850_CL1, +}; /** * struct exynos_cpuclk_cfg_data - config data to setup cpu clocks @@ -28,38 +45,4 @@ struct exynos_cpuclk_cfg_data { unsigned long div1; }; -/** - * struct exynos_cpuclk - information about clock supplied to a CPU core - * @hw: handle between CCF and CPU clock - * @alt_parent: alternate parent clock to use when switching the speed - * of the primary parent clock - * @ctrl_base: base address of the clock controller - * @lock: cpu clock domain register access lock - * @cfg: cpu clock rate configuration data - * @num_cfgs: number of array elements in @cfg array - * @clk_nb: clock notifier registered for changes in clock speed of the - * primary parent clock - * @flags: configuration flags for the CPU clock - * - * This structure holds information required for programming the CPU clock for - * various clock speeds. - */ -struct exynos_cpuclk { - struct clk_hw hw; - const struct clk_hw *alt_parent; - void __iomem *ctrl_base; - spinlock_t *lock; - const struct exynos_cpuclk_cfg_data *cfg; - const unsigned long num_cfgs; - struct notifier_block clk_nb; - unsigned long flags; - -/* The CPU clock registers have DIV1 configuration register */ -#define CLK_CPU_HAS_DIV1 (1 << 0) -/* When ALT parent is active, debug clocks need safe divider values */ -#define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1) -/* The CPU clock registers have Exynos5433-compatible layout */ -#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2) -}; - #endif /* __SAMSUNG_CLK_CPU_H */ diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index a02461667664..cd4fec323a42 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -775,7 +775,7 @@ static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = { static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C, - CLK_CPU_HAS_DIV1, 0x14200, e3250_armclk_d), + CLK_CPU_HAS_DIV1, 0x14000, CPUCLK_LAYOUT_E4210, e3250_armclk_d), }; static void __init exynos3_core_down_clock(void __iomem *reg_base) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 4ec41221e68f..a026ccca7315 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1252,17 +1252,20 @@ static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL, - CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d), + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000, + CPUCLK_LAYOUT_E4210, e4210_armclk_d), }; static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C, - CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4212_armclk_d), + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000, + CPUCLK_LAYOUT_E4210, e4212_armclk_d), }; static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C, - CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d), + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000, + CPUCLK_LAYOUT_E4210, e4412_armclk_d), }; /* register exynos4 clocks */ diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 8ebe6155d8b7..e02e7c013f3d 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -776,8 +776,9 @@ static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = { }; static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = { - CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL, CLK_CPU_HAS_DIV1, 0x200, - exynos5250_armclk_d), + CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL, + CLK_CPU_HAS_DIV1, 0x0, CPUCLK_LAYOUT_E4210, + exynos5250_armclk_d), }; static const struct of_device_id ext_clk_match[] __initconst = { diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 199843f12ae5..c630135c686b 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1555,17 +1555,17 @@ static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { }; static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = { - CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200, - exynos5420_eglclk_d), - CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200, - exynos5420_kfcclk_d), + CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, + 0x0, CPUCLK_LAYOUT_E4210, exynos5420_eglclk_d), + CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, + 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d), }; static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = { - CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200, - exynos5800_eglclk_d), - CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200, - exynos5420_kfcclk_d), + CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, + 0x0, CPUCLK_LAYOUT_E4210, exynos5800_eglclk_d), + CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, + 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d), }; static const struct of_device_id ext_clk_match[] __initconst = { diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 6bfc5d0cd924..609d31a7aa52 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -3700,9 +3700,8 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = { CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL, - CLK_MOUT_BUS_PLL_APOLLO_USER, - CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200, - exynos5433_apolloclk_d), + CLK_MOUT_BUS_PLL_APOLLO_USER, 0, 0x0, + CPUCLK_LAYOUT_E5433, exynos5433_apolloclk_d), }; static const struct samsung_cmu_info apollo_cmu_info __initconst = { @@ -3945,9 +3944,8 @@ static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = { CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL, - CLK_MOUT_BUS_PLL_ATLAS_USER, - CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200, - exynos5433_atlasclk_d), + CLK_MOUT_BUS_PLL_ATLAS_USER, 0, 0x0, + CPUCLK_LAYOUT_E5433, exynos5433_atlasclk_d), }; static const struct samsung_cmu_info atlas_cmu_info __initconst = { diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index bdc1eef7d6e5..82cfa22c0788 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -26,7 +26,7 @@ #define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1) #define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1) #define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1) -#define CLKS_NR_CORE (CLK_GOUT_SYSREG_CORE_PCLK + 1) +#define CLKS_NR_CORE (CLK_GOUT_SPDMA_CORE_ACLK + 1) #define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1) /* ---- CMU_TOP ------------------------------------------------------------- */ @@ -605,7 +605,7 @@ static const struct samsung_div_clock apm_div_clks[] __initconst = { static const struct samsung_gate_clock apm_gate_clks[] __initconst = { GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", - CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), + CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", "mout_clkcmu_chub_bus", CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), @@ -974,19 +974,19 @@ static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = { static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), - MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, - CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), - MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, - CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), + MUX_F(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1, CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1, CLK_SET_RATE_PARENT, 0), }; static const struct samsung_div_clock cmgp_div_clks[] __initconst = { DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), - DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", - CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), - DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", - CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), + DIV_F(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", + CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", + CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5, CLK_SET_RATE_PARENT, 0), }; static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { @@ -1001,12 +1001,12 @@ static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { "gout_clkcmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", - CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), + CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", "gout_clkcmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", - CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), + CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", "gout_clkcmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), @@ -1557,8 +1557,9 @@ static const struct samsung_mux_clock peri_mux_clks[] __initconst = { mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), - MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, - PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), + MUX_F(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", + mout_peri_spi_user_p, PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1, + CLK_SET_RATE_PARENT, 0), }; static const struct samsung_div_clock peri_div_clks[] __initconst = { @@ -1568,8 +1569,8 @@ static const struct samsung_div_clock peri_div_clks[] __initconst = { CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), - DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", - CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), + DIV_F(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", + CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5, CLK_SET_RATE_PARENT, 0), }; static const struct samsung_gate_clock peri_gate_clks[] __initconst = { @@ -1611,7 +1612,7 @@ static const struct samsung_gate_clock peri_gate_clks[] __initconst = { "mout_peri_bus_user", CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", - CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), + CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", @@ -1667,6 +1668,8 @@ CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec +#define CLK_CON_GAT_GOUT_CORE_PDMA_ACLK 0x20f0 +#define CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK 0x2124 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 @@ -1683,6 +1686,8 @@ static const unsigned long core_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, + CLK_CON_GAT_GOUT_CORE_PDMA_ACLK, + CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK, CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, @@ -1726,6 +1731,10 @@ static const struct samsung_gate_clock core_gate_clks[] __initconst = { GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PDMA_CORE_ACLK, "gout_pdma_core_aclk", + "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_PDMA_ACLK, 21, 0, 0), + GATE(CLK_GOUT_SPDMA_CORE_ACLK, "gout_spdma_core_aclk", + "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK, 21, 0, 0), GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 0964bb11657f..d065e343a85d 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -20,11 +20,12 @@ #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) +#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) /* ---- CMU_TOP ------------------------------------------------------------- */ /* Register Offset definitions for CMU_TOP (0x1e080000) */ - #define PLL_LOCKTIME_PLL_SHARED0 0x0000 #define PLL_LOCKTIME_PLL_SHARED1 0x0004 #define PLL_LOCKTIME_PLL_SHARED2 0x0008 @@ -2475,7 +2476,937 @@ static const struct samsung_cmu_info misc_cmu_info __initconst = { .nr_clk_ids = CLKS_NR_MISC, .clk_regs = misc_clk_regs, .nr_clk_regs = ARRAY_SIZE(misc_clk_regs), - .clk_name = "dout_cmu_misc_bus", + .clk_name = "bus", +}; + +static void __init gs101_cmu_misc_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &misc_cmu_info); +} + +/* Register CMU_MISC early, as it's needed for MCT timer */ +CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc", + gs101_cmu_misc_init); + +/* ---- CMU_PERIC0 ---------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC0 (0x10800000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4 +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0 +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4 +#define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800 +#define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834 +#define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4 +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c +#define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018 +#define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c +#define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020 +#define QCH_CON_D_TZPC_PERIC0_QCH 0x3024 +#define QCH_CON_GPC_PERIC0_QCH 0x3028 +#define QCH_CON_GPIO_PERIC0_QCH 0x302c +#define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030 +#define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034 +#define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038 +#define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c +#define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040 +#define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044 +#define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048 +#define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c +#define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050 +#define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054 +#define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058 +#define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c +#define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060 +#define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064 +#define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068 +#define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c +#define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070 +#define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074 +#define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078 +#define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c +#define QCH_CON_SYSREG_PERIC0_QCH 0x3080 +#define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00 + +static const unsigned long peric0_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER, + PERIC0_CMU_PERIC0_CONTROLLER_OPTION, + CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0, + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, + CLK_CON_BUF_CLKBUF_PERIC0_IP, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + DMYQCH_CON_PERIC0_TOP0_QCH_S1, + DMYQCH_CON_PERIC0_TOP0_QCH_S2, + DMYQCH_CON_PERIC0_TOP0_QCH_S3, + DMYQCH_CON_PERIC0_TOP0_QCH_S4, + DMYQCH_CON_PERIC0_TOP0_QCH_S5, + DMYQCH_CON_PERIC0_TOP0_QCH_S6, + DMYQCH_CON_PERIC0_TOP0_QCH_S7, + DMYQCH_CON_PERIC0_TOP0_QCH_S8, + PCH_CON_LHM_AXI_P_PERIC0_PCH, + QCH_CON_D_TZPC_PERIC0_QCH, + QCH_CON_GPC_PERIC0_QCH, + QCH_CON_GPIO_PERIC0_QCH, + QCH_CON_LHM_AXI_P_PERIC0_QCH, + QCH_CON_PERIC0_CMU_PERIC0_QCH, + QCH_CON_PERIC0_TOP0_QCH_I3C1, + QCH_CON_PERIC0_TOP0_QCH_I3C2, + QCH_CON_PERIC0_TOP0_QCH_I3C3, + QCH_CON_PERIC0_TOP0_QCH_I3C4, + QCH_CON_PERIC0_TOP0_QCH_I3C5, + QCH_CON_PERIC0_TOP0_QCH_I3C6, + QCH_CON_PERIC0_TOP0_QCH_I3C7, + QCH_CON_PERIC0_TOP0_QCH_I3C8, + QCH_CON_PERIC0_TOP0_QCH_USI1_USI, + QCH_CON_PERIC0_TOP0_QCH_USI2_USI, + QCH_CON_PERIC0_TOP0_QCH_USI3_USI, + QCH_CON_PERIC0_TOP0_QCH_USI4_USI, + QCH_CON_PERIC0_TOP0_QCH_USI5_USI, + QCH_CON_PERIC0_TOP0_QCH_USI6_USI, + QCH_CON_PERIC0_TOP0_QCH_USI7_USI, + QCH_CON_PERIC0_TOP0_QCH_USI8_USI, + QCH_CON_PERIC0_TOP1_QCH_USI0_UART, + QCH_CON_PERIC0_TOP1_QCH_USI14_UART, + QCH_CON_SYSREG_PERIC0_QCH, + QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0, +}; + +/* List of parent clocks for Muxes in CMU_PERIC0 */ +PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" }; +PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; +PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; + +static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", + mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user", + mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI0_UART_USER, + "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI14_USI_USER, + "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI1_USI_USER, + "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI2_USI_USER, + "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI3_USI_USER, + "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI4_USI_USER, + "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI5_USI_USER, + "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI6_USI_USER, + "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI7_USI_USER, + "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_USI8_USI_USER, + "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), +}; + +static const struct samsung_div_clock peric0_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user", + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4), + DIV(CLK_DOUT_PERIC0_USI0_UART, + "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4), + DIV(CLK_DOUT_PERIC0_USI14_USI, + "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI1_USI, + "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI2_USI, + "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI3_USI, + "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI4_USI, + "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI5_USI, + "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI6_USI, + "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI7_USI, + "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4), + DIV(CLK_DOUT_PERIC0_USI8_USI, + "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4), +}; + +static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK, + "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK, + "gout_peric0_clk_peric0_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK, + "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK, + "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, + "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, + "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, + "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1, + "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10, + "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11, + "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12, + "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13, + "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14, + "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15, + "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2, + "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3, + "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4, + "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5, + "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6, + "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7, + "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8, + "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9, + "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0, + "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1, + "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10, + "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11, + "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12, + "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13, + "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14, + "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15, + "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2, + "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3, + "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4, + "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5, + "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6, + "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7, + "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8, + "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9, + "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, + 21, 0, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, + "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, + "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, + 21, 0, 0), + /* Disabling this clock makes the system hang. Mark the clock as critical. */ + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, + "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, + "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK, + "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK, + "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK, + "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK, + "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK, + "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK, + "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK, + "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK, + "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK, + "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK, + "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK, + "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK, + "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK, + "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info peric0_cmu_info __initconst = { + .mux_clks = peric0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), + .div_clks = peric0_div_clks, + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), + .gate_clks = peric0_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), + .nr_clk_ids = CLKS_NR_PERIC0, + .clk_regs = peric0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), + .clk_name = "bus", +}; + +/* ---- CMU_PERIC1 ---------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC1 (0x10c00000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674 +#define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800 +#define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810 +#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818 +#define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078 +#define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000 +#define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004 +#define QCH_CON_D_TZPC_PERIC1_QCH 0x3008 +#define QCH_CON_GPC_PERIC1_QCH 0x300c +#define QCH_CON_GPIO_PERIC1_QCH 0x3010 +#define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014 +#define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018 +#define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c +#define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020 +#define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024 +#define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028 +#define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c +#define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030 +#define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034 +#define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038 +#define QCH_CON_SYSREG_PERIC1_QCH 0x303c +#define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00 + +static const unsigned long peric1_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER, + PERIC1_CMU_PERIC1_CONTROLLER_OPTION, + CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0, + CLK_CON_DIV_DIV_CLK_PERIC1_I3C, + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, + CLK_CON_BUF_CLKBUF_PERIC1_IP, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + DMYQCH_CON_PERIC1_TOP0_QCH_S, + PCH_CON_LHM_AXI_P_PERIC1_PCH, + QCH_CON_D_TZPC_PERIC1_QCH, + QCH_CON_GPC_PERIC1_QCH, + QCH_CON_GPIO_PERIC1_QCH, + QCH_CON_LHM_AXI_P_PERIC1_QCH, + QCH_CON_PERIC1_CMU_PERIC1_QCH, + QCH_CON_PERIC1_TOP0_QCH_I3C0, + QCH_CON_PERIC1_TOP0_QCH_PWM, + QCH_CON_PERIC1_TOP0_QCH_USI0_USI, + QCH_CON_PERIC1_TOP0_QCH_USI10_USI, + QCH_CON_PERIC1_TOP0_QCH_USI11_USI, + QCH_CON_PERIC1_TOP0_QCH_USI12_USI, + QCH_CON_PERIC1_TOP0_QCH_USI13_USI, + QCH_CON_PERIC1_TOP0_QCH_USI9_USI, + QCH_CON_SYSREG_PERIC1_QCH, + QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1, +}; + +/* List of parent clocks for Muxes in CMU_PERIC1 */ +PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" }; +PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" }; + +static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user", + mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_I3C_USER, + "mout_peric1_i3c_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI0_USI_USER, + "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI10_USI_USER, + "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI11_USI_USER, + "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI12_USI_USER, + "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI13_USI_USER, + "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI9_USI_USER, + "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1), +}; + +static const struct samsung_div_clock peric1_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user", + CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4), + DIV(CLK_DOUT_PERIC1_USI0_USI, + "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI10_USI, + "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI11_USI, + "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI12_USI, + "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI13_USI, + "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI9_USI, + "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4), +}; + +static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { + GATE(CLK_GOUT_PERIC1_PCLK, + "gout_peric1_peric1_pclk", "mout_peric1_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK, + "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK, + "gout_peric1_clk_peric1_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK, + "gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK, + "gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK, + "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK, + "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1, + "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2, + "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3, + "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4, + "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5, + "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6, + "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8, + "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1, + "gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15, + "gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2, + "gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3, + "gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4, + "gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5, + "gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6, + "gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8, + "gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK, + "gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK, + "gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK, + "gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK, + "gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK, + "gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK, + "gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK, + "gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK, + "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info peric1_cmu_info __initconst = { + .mux_clks = peric1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), + .div_clks = peric1_div_clks, + .nr_div_clks = ARRAY_SIZE(peric1_div_clks), + .gate_clks = peric1_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), + .nr_clk_ids = CLKS_NR_PERIC1, + .clk_regs = peric1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), + .clk_name = "bus", }; /* ---- platform_driver ----------------------------------------------------- */ @@ -2496,8 +3427,11 @@ static const struct of_device_id gs101_cmu_of_match[] = { .compatible = "google,gs101-cmu-apm", .data = &apm_cmu_info, }, { - .compatible = "google,gs101-cmu-misc", - .data = &misc_cmu_info, + .compatible = "google,gs101-cmu-peric0", + .data = &peric0_cmu_info, + }, { + .compatible = "google,gs101-cmu-peric1", + .data = &peric1_cmu_info, }, { }, }; diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 516b716407e5..a763309e6f12 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -12,6 +12,7 @@ #include <linux/clk-provider.h> #include "clk-pll.h" +#include "clk-cpu.h" /** * struct samsung_clk_provider - information about clock provider @@ -282,10 +283,11 @@ struct samsung_cpu_clock { unsigned int alt_parent_id; unsigned long flags; int offset; + enum exynos_cpuclk_layout reg_layout; const struct exynos_cpuclk_cfg_data *cfg; }; -#define CPU_CLK(_id, _name, _pid, _apid, _flags, _offset, _cfg) \ +#define CPU_CLK(_id, _name, _pid, _apid, _flags, _offset, _layout, _cfg) \ { \ .id = _id, \ .name = _name, \ @@ -293,6 +295,7 @@ struct samsung_cpu_clock { .alt_parent_id = _apid, \ .flags = _flags, \ .offset = _offset, \ + .reg_layout = _layout, \ .cfg = _cfg, \ } diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index 3090e09c9a55..7666241520f8 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -88,6 +88,18 @@ #define CLK_MOUT_G3D_SWITCH 76 #define CLK_GOUT_G3D_SWITCH 77 #define CLK_DOUT_G3D_SWITCH 78 +#define CLK_MOUT_CPUCL0_DBG 79 +#define CLK_MOUT_CPUCL0_SWITCH 80 +#define CLK_GOUT_CPUCL0_DBG 81 +#define CLK_GOUT_CPUCL0_SWITCH 82 +#define CLK_DOUT_CPUCL0_DBG 83 +#define CLK_DOUT_CPUCL0_SWITCH 84 +#define CLK_MOUT_CPUCL1_DBG 85 +#define CLK_MOUT_CPUCL1_SWITCH 86 +#define CLK_GOUT_CPUCL1_DBG 87 +#define CLK_GOUT_CPUCL1_SWITCH 88 +#define CLK_DOUT_CPUCL1_DBG 89 +#define CLK_DOUT_CPUCL1_SWITCH 90 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -195,6 +207,48 @@ #define CLK_GOUT_CMGP_USI1_PCLK 14 #define CLK_GOUT_SYSREG_CMGP_PCLK 15 +/* CMU_CPUCL0 */ +#define CLK_FOUT_CPUCL0_PLL 1 +#define CLK_MOUT_PLL_CPUCL0 2 +#define CLK_MOUT_CPUCL0_SWITCH_USER 3 +#define CLK_MOUT_CPUCL0_DBG_USER 4 +#define CLK_MOUT_CPUCL0_PLL 5 +#define CLK_DOUT_CPUCL0_CPU 6 +#define CLK_DOUT_CPUCL0_CMUREF 7 +#define CLK_DOUT_CPUCL0_PCLK 8 +#define CLK_DOUT_CLUSTER0_ACLK 9 +#define CLK_DOUT_CLUSTER0_ATCLK 10 +#define CLK_DOUT_CLUSTER0_PCLKDBG 11 +#define CLK_DOUT_CLUSTER0_PERIPHCLK 12 +#define CLK_GOUT_CLUSTER0_ATCLK 13 +#define CLK_GOUT_CLUSTER0_PCLK 14 +#define CLK_GOUT_CLUSTER0_PERIPHCLK 15 +#define CLK_GOUT_CLUSTER0_SCLK 16 +#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK 17 +#define CLK_GOUT_CLUSTER0_CPU 18 +#define CLK_CLUSTER0_SCLK 19 + +/* CMU_CPUCL1 */ +#define CLK_FOUT_CPUCL1_PLL 1 +#define CLK_MOUT_PLL_CPUCL1 2 +#define CLK_MOUT_CPUCL1_SWITCH_USER 3 +#define CLK_MOUT_CPUCL1_DBG_USER 4 +#define CLK_MOUT_CPUCL1_PLL 5 +#define CLK_DOUT_CPUCL1_CPU 6 +#define CLK_DOUT_CPUCL1_CMUREF 7 +#define CLK_DOUT_CPUCL1_PCLK 8 +#define CLK_DOUT_CLUSTER1_ACLK 9 +#define CLK_DOUT_CLUSTER1_ATCLK 10 +#define CLK_DOUT_CLUSTER1_PCLKDBG 11 +#define CLK_DOUT_CLUSTER1_PERIPHCLK 12 +#define CLK_GOUT_CLUSTER1_ATCLK 13 +#define CLK_GOUT_CLUSTER1_PCLK 14 +#define CLK_GOUT_CLUSTER1_PERIPHCLK 15 +#define CLK_GOUT_CLUSTER1_SCLK 16 +#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK 17 +#define CLK_GOUT_CLUSTER1_CPU 18 +#define CLK_CLUSTER1_SCLK 19 + /* CMU_G3D */ #define CLK_FOUT_G3D_PLL 1 #define CLK_MOUT_G3D_PLL 2 @@ -320,6 +374,8 @@ #define CLK_GOUT_SSS_PCLK 12 #define CLK_GOUT_GPIO_CORE_PCLK 13 #define CLK_GOUT_SYSREG_CORE_PCLK 14 +#define CLK_GOUT_PDMA_CORE_ACLK 15 +#define CLK_GOUT_SPDMA_CORE_ACLK 16 /* CMU_DPU */ #define CLK_MOUT_DPU_USER 1 diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 21adec22387c..3dac3577788a 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -389,4 +389,133 @@ #define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73 #define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74 +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_I3C_USER 2 +#define CLK_MOUT_PERIC0_USI0_UART_USER 3 +#define CLK_MOUT_PERIC0_USI14_USI_USER 4 +#define CLK_MOUT_PERIC0_USI1_USI_USER 5 +#define CLK_MOUT_PERIC0_USI2_USI_USER 6 +#define CLK_MOUT_PERIC0_USI3_USI_USER 7 +#define CLK_MOUT_PERIC0_USI4_USI_USER 8 +#define CLK_MOUT_PERIC0_USI5_USI_USER 9 +#define CLK_MOUT_PERIC0_USI6_USI_USER 10 +#define CLK_MOUT_PERIC0_USI7_USI_USER 11 +#define CLK_MOUT_PERIC0_USI8_USI_USER 12 +#define CLK_DOUT_PERIC0_I3C 13 +#define CLK_DOUT_PERIC0_USI0_UART 14 +#define CLK_DOUT_PERIC0_USI14_USI 15 +#define CLK_DOUT_PERIC0_USI1_USI 16 +#define CLK_DOUT_PERIC0_USI2_USI 17 +#define CLK_DOUT_PERIC0_USI3_USI 18 +#define CLK_DOUT_PERIC0_USI4_USI 19 +#define CLK_DOUT_PERIC0_USI5_USI 20 +#define CLK_DOUT_PERIC0_USI6_USI 21 +#define CLK_DOUT_PERIC0_USI7_USI 22 +#define CLK_DOUT_PERIC0_USI8_USI 23 +#define CLK_GOUT_PERIC0_IP 24 +#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25 +#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26 +#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27 +#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28 +#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29 +#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66 +#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67 +#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK 72 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK 73 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK 74 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK 75 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK 76 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK 77 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78 +#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_BUS_USER 1 +#define CLK_MOUT_PERIC1_I3C_USER 2 +#define CLK_MOUT_PERIC1_USI0_USI_USER 3 +#define CLK_MOUT_PERIC1_USI10_USI_USER 4 +#define CLK_MOUT_PERIC1_USI11_USI_USER 5 +#define CLK_MOUT_PERIC1_USI12_USI_USER 6 +#define CLK_MOUT_PERIC1_USI13_USI_USER 7 +#define CLK_MOUT_PERIC1_USI9_USI_USER 8 +#define CLK_DOUT_PERIC1_I3C 9 +#define CLK_DOUT_PERIC1_USI0_USI 10 +#define CLK_DOUT_PERIC1_USI10_USI 11 +#define CLK_DOUT_PERIC1_USI11_USI 12 +#define CLK_DOUT_PERIC1_USI12_USI 13 +#define CLK_DOUT_PERIC1_USI13_USI 14 +#define CLK_DOUT_PERIC1_USI9_USI 15 +#define CLK_GOUT_PERIC1_IP 16 +#define CLK_GOUT_PERIC1_PCLK 17 +#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18 +#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19 +#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20 +#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21 +#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22 +#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38 +#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45 +#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ |