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| author | John Rigby <jrigby@freescale.com> | 2008-01-18 03:05:32 +0300 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-01-24 04:34:24 +0300 |
| commit | a7267d679fc5a2f1d3f3f247e22a9824f17b507a (patch) | |
| tree | 92a31efe5fb5c2181161c35b94c59d443c582276 | |
| parent | e3bc3a09bdfc1b3b88b32d7960c4c3b84a2b860f (diff) | |
| download | linux-a7267d679fc5a2f1d3f3f247e22a9824f17b507a.tar.xz | |
[POWERPC] Add support for mpc512x interrupts to ipic
Added ipic_info entries for vectors used by 512x that
were previously unused by 83xx.
Signed-off-by: John Rigby <jrigby@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | arch/powerpc/sysdev/ipic.c | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c index 7274750fd9c6..4c016da68426 100644 --- a/arch/powerpc/sysdev/ipic.c +++ b/arch/powerpc/sysdev/ipic.c @@ -48,6 +48,13 @@ static struct ipic_info ipic_info[] = { .bit = 17, .prio_mask = 1, }, + [3] = { + .mask = IPIC_SIMSR_H, + .prio = IPIC_SIPRR_C, + .force = IPIC_SIFCR_H, + .bit = 18, + .prio_mask = 2, + }, [4] = { .mask = IPIC_SIMSR_H, .prio = IPIC_SIPRR_C, @@ -55,6 +62,34 @@ static struct ipic_info ipic_info[] = { .bit = 19, .prio_mask = 3, }, + [5] = { + .mask = IPIC_SIMSR_H, + .prio = IPIC_SIPRR_C, + .force = IPIC_SIFCR_H, + .bit = 20, + .prio_mask = 4, + }, + [6] = { + .mask = IPIC_SIMSR_H, + .prio = IPIC_SIPRR_C, + .force = IPIC_SIFCR_H, + .bit = 21, + .prio_mask = 5, + }, + [7] = { + .mask = IPIC_SIMSR_H, + .prio = IPIC_SIPRR_C, + .force = IPIC_SIFCR_H, + .bit = 22, + .prio_mask = 6, + }, + [8] = { + .mask = IPIC_SIMSR_H, + .prio = IPIC_SIPRR_C, + .force = IPIC_SIFCR_H, + .bit = 23, + .prio_mask = 7, + }, [9] = { .mask = IPIC_SIMSR_H, .prio = IPIC_SIPRR_D, @@ -223,6 +258,20 @@ static struct ipic_info ipic_info[] = { .bit = 7, .prio_mask = 7, }, + [40] = { + .mask = IPIC_SIMSR_H, + .prio = IPIC_SIPRR_B, + .force = IPIC_SIFCR_H, + .bit = 8, + .prio_mask = 0, + }, + [41] = { + .mask = IPIC_SIMSR_H, + .prio = IPIC_SIPRR_B, + .force = IPIC_SIFCR_H, + .bit = 9, + .prio_mask = 1, + }, [42] = { .mask = IPIC_SIMSR_H, .prio = IPIC_SIPRR_B, @@ -230,6 +279,13 @@ static struct ipic_info ipic_info[] = { .bit = 10, .prio_mask = 2, }, + [43] = { + .mask = IPIC_SIMSR_H, + .prio = IPIC_SIPRR_B, + .force = IPIC_SIFCR_H, + .bit = 11, + .prio_mask = 3, + }, [44] = { .mask = IPIC_SIMSR_H, .prio = IPIC_SIPRR_B, @@ -387,6 +443,12 @@ static struct ipic_info ipic_info[] = { .force = IPIC_SIFCR_L, .bit = 18, }, + [83] = { + .mask = IPIC_SIMSR_L, + .prio = 0, + .force = IPIC_SIFCR_L, + .bit = 19, + }, [84] = { .mask = IPIC_SIMSR_L, .prio = 0, |