diff options
| author | Florian Fainelli <f.fainelli@gmail.com> | 2014-03-25 03:36:48 +0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-03-27 00:19:24 +0400 |
| commit | 9918542e2d02f259f909a956e41bd6d5827fa422 (patch) | |
| tree | d0be668523442a9793db20a01dd370eb44a66ff5 | |
| parent | a3622f2c824135a7ce235a61bf9ff5688e8f576b (diff) | |
| download | linux-9918542e2d02f259f909a956e41bd6d5827fa422.tar.xz | |
net: phy: bcm7xxx: fix spurious MDIO failures during workaround
Writing first to the AFE registers, and then the VCO, RCAL, RC_CAL
registers turned out to unveil some spurious MDIO read/write failures
which would make the workaround partially applied. The fix is to write
first to the VCO, RCAL, RC_CAL registers, and then write to the AFE
registers.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/phy/bcm7xxx.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/net/phy/bcm7xxx.c b/drivers/net/phy/bcm7xxx.c index 314194179168..5991168bcbef 100644 --- a/drivers/net/phy/bcm7xxx.c +++ b/drivers/net/phy/bcm7xxx.c @@ -103,21 +103,6 @@ static void phy_write_misc(struct phy_device *phydev, static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev) { - /* write AFE_RXCONFIG_0 */ - phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19); - - /* write AFE_RXCONFIG_1 */ - phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f); - - /* write AFE_RX_LP_COUNTER */ - phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc7); - - /* write AFE_HPF_TRIM_OTHERS */ - phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b); - - /* write AFTE_TX_CONFIG */ - phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800); - /* Increase VCO range to prevent unlocking problem of PLL at low * temp */ @@ -143,6 +128,21 @@ static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev) /* Disable Reset R_CAL/RC_CAL Engine */ phy_write_exp(phydev, CORE_EXPB0, 0x0000); + /* write AFE_RXCONFIG_0 */ + phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19); + + /* write AFE_RXCONFIG_1 */ + phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f); + + /* write AFE_RX_LP_COUNTER */ + phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc7); + + /* write AFE_HPF_TRIM_OTHERS */ + phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b); + + /* write AFTE_TX_CONFIG */ + phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800); + return 0; } |