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| author | Daniel Palmer <daniel@0x0f.com> | 2020-10-02 16:34:15 +0300 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2020-10-03 22:48:08 +0300 |
| commit | 925595f77f8bcf0159d9ff97141eeb1fed506888 (patch) | |
| tree | e1674327756954e7df002d4b679484c285ebc0b4 | |
| parent | 5c505432deb545580b41fa6d751721f319974f13 (diff) | |
| download | linux-925595f77f8bcf0159d9ff97141eeb1fed506888.tar.xz | |
ARM: mstar: Add interrupt controller to base dtsi
Add the IRQ and FIQ intc instances to the base MStar/SigmaStar v7
dtsi. All of the known SoCs have both and at the same place with
their common IPs using the same interrupt lines.
Link: https://lore.kernel.org/r/20201002133418.2250277-3-daniel@0x0f.com
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
| -rw-r--r-- | arch/arm/boot/dts/mstar-v7.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3b7b9b793736..aec841b52ca4 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -85,6 +85,25 @@ mask = <0x79>; }; + intc_fiq: interrupt-controller@201310 { + compatible = "mstar,mst-intc"; + reg = <0x201310 0x40>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + mstar,irqs-map-range = <96 127>; + }; + + intc_irq: interrupt-controller@201350 { + compatible = "mstar,mst-intc"; + reg = <0x201350 0x40>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + mstar,irqs-map-range = <32 95>; + mstar,intc-no-eoi; + }; + l3bridge: l3bridge@204400 { compatible = "mstar,l3bridge"; reg = <0x204400 0x200>; |