diff options
| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2022-10-26 10:45:30 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2022-11-07 07:50:25 +0300 |
| commit | 8ca2a81bff096b359736bba9b7d06cf5bc04fa88 (patch) | |
| tree | 26fb62201ce87388936a3769f4213f0d687fa8e5 | |
| parent | 0f607406525d25019dd9c498bcc0b42734fc59d5 (diff) | |
| download | linux-8ca2a81bff096b359736bba9b7d06cf5bc04fa88.tar.xz | |
dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e
TI's J721e SoC supports additional PHY modes like QSGMII and SGMII
that are not supported on earlier SoCs. Add a compatible for it.
Extend ti,qsgmii-main-ports property to support selection of upto
two main ports at once across the two QSGMII interfaces.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221026074532.109220-2-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml | 48 |
1 files changed, 42 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml index da7cac537e15..3a6d686383cf 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml @@ -54,6 +54,7 @@ properties: - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel reg: maxItems: 1 @@ -63,14 +64,17 @@ properties: ti,qsgmii-main-ports: $ref: /schemas/types.yaml#/definitions/uint32-array description: | - Required only for QSGMII mode. Array to select the port for - QSGMII main mode. Rest of the ports are selected as QSGMII_SUB - ports automatically. Any one of the 4 CPSW5G ports can act as the - main port with the rest of them being the QSGMII_SUB ports. - maxItems: 1 + Required only for QSGMII mode. Array to select the port/s for QSGMII + main mode. The size of the array corresponds to the number of QSGMII + interfaces and thus, the number of distinct QSGMII main ports, + supported by the device. If the device supports two QSGMII interfaces + but only one QSGMII interface is desired, repeat the QSGMII main port + value corresponding to the QSGMII interface in the array. + minItems: 1 + maxItems: 2 items: minimum: 1 - maximum: 4 + maximum: 8 allOf: - if: @@ -81,6 +85,8 @@ allOf: - ti,dra7xx-phy-gmii-sel - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel + - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel then: properties: '#phy-cells': @@ -88,12 +94,42 @@ allOf: description: CPSW port number (starting from 1) - if: + properties: + compatible: + contains: + enum: + - ti,j7200-cpsw5g-phy-gmii-sel + then: + properties: + ti,qsgmii-main-ports: + maxItems: 1 + items: + minimum: 1 + maximum: 4 + + - if: + properties: + compatible: + contains: + enum: + - ti,j721e-cpsw9g-phy-gmii-sel + then: + properties: + ti,qsgmii-main-ports: + minItems: 2 + maxItems: 2 + items: + minimum: 1 + maximum: 8 + + - if: not: properties: compatible: contains: enum: - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel then: properties: ti,qsgmii-main-ports: false |