diff options
| author | Noam Camus <noamca@mellanox.com> | 2017-05-28 09:52:06 +0300 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2017-08-29 01:17:36 +0300 |
| commit | 644fa02b392e25d7592951da2b2b64b4d533d1be (patch) | |
| tree | 478eb451af152ed2ea0349f8c217602af9405523 | |
| parent | 64f42cec84deb32fdaf24649481c72fcd7800dc1 (diff) | |
| download | linux-644fa02b392e25d7592951da2b2b64b4d533d1be.tar.xz | |
ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle task
When HW threads are active we want CPU to enter idle state only
for the calling HW thread and not to put on sleep all HW threads
sharing this core. For this need the NPS400 got dedicated instruction
so only calling thread is entring sleep and all other are still awake
and can execute instructions.
Signed-off-by: Noam Camus <noamca@mellanox.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
[vgupta: reworked patch to not use inline ifdef but a new function itself]
| -rw-r--r-- | arch/arc/kernel/process.c | 13 | ||||
| -rw-r--r-- | arch/arc/plat-eznps/include/plat/ctop.h | 1 |
2 files changed, 13 insertions, 1 deletions
diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c index fd5b2190a957..5c631a111240 100644 --- a/arch/arc/kernel/process.c +++ b/arch/arc/kernel/process.c @@ -92,7 +92,18 @@ void arch_cpu_idle(void) :"I"(arg)); /* can't be "r" has to be embedded const */ } -#else +#elif defined(CONFIG_EZNPS_MTM_EXT) /* ARC700 variant in NPS */ + +void arch_cpu_idle(void) +{ + /* only the calling HW thread needs to sleep */ + __asm__ __volatile__( + ".word %0 \n" + : + :"i"(CTOP_INST_HWSCHD_WFT_IE12)); +} + +#else /* ARC700 */ void arch_cpu_idle(void) { diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h index ee2e32df5e90..7729d3d18300 100644 --- a/arch/arc/plat-eznps/include/plat/ctop.h +++ b/arch/arc/plat-eznps/include/plat/ctop.h @@ -46,6 +46,7 @@ #define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300) /* EZchip core instructions */ +#define CTOP_INST_HWSCHD_WFT_IE12 0x3E6F7344 #define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF #define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103 #define CTOP_INST_SCHD_RW 0x3E6F7004 |