diff options
| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2020-09-11 20:31:38 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-09-22 00:08:34 +0300 |
| commit | 5b4458ebb4c8007dae7eaeb88cb52b2bb4879894 (patch) | |
| tree | 7fbcf3b8d0c6d5843d39f66b4a39d3d42d67db30 | |
| parent | 501ef013390b774e8e61000a78d1d640d6c3411d (diff) | |
| download | linux-5b4458ebb4c8007dae7eaeb88cb52b2bb4879894.tar.xz | |
ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilization
As indicated in the datasheet, a 10ms delay must be observed after
programming the divisors.
The lack of delay prevents the codec to work properly and the playback
appears extremely slow and totally un-audible on a custom sama5 based
board.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20200911173140.29984-2-miquel.raynal@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | sound/soc/codecs/tlv320aic32x4-clk.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/sound/soc/codecs/tlv320aic32x4-clk.c b/sound/soc/codecs/tlv320aic32x4-clk.c index 156c153c12ab..2f78e6820c75 100644 --- a/sound/soc/codecs/tlv320aic32x4-clk.c +++ b/sound/soc/codecs/tlv320aic32x4-clk.c @@ -230,7 +230,14 @@ static int clk_aic32x4_pll_set_rate(struct clk_hw *hw, if (ret < 0) return -EINVAL; - return clk_aic32x4_pll_set_muldiv(pll, &settings); + ret = clk_aic32x4_pll_set_muldiv(pll, &settings); + if (ret) + return ret; + + /* 10ms is the delay to wait before the clocks are stable */ + msleep(10); + + return 0; } static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index) |