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| author | Chunfeng Yun <chunfeng.yun@mediatek.com> | 2017-09-21 13:31:48 +0300 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2017-09-26 14:32:48 +0300 |
| commit | 554a56fc83f679c73b4f851a330045d0ec7ec1a5 (patch) | |
| tree | 5a5e86fcafc0870a268758eeb022b7a3e3969974 | |
| parent | 1df79cb3bae754e4a42240f9851ed82549a44f1a (diff) | |
| download | linux-554a56fc83f679c73b4f851a330045d0ec7ec1a5.tar.xz | |
phy: phy-mtk-tphy: fix NULL point of chip bank
Chip bank of version-1 is initialized as NULL, but it's used
by pcie_phy_instance_power_on/off(), so assign it a right
address.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| -rw-r--r-- | drivers/phy/mediatek/phy-mtk-tphy.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index e3baad78521f..721a2a1c97ef 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -27,6 +27,7 @@ /* banks shared by multiple phys */ #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ +#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ /* u2 phy bank */ #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 /* u3/pcie/sata phy banks */ @@ -762,7 +763,7 @@ static void phy_v1_banks_init(struct mtk_tphy *tphy, case PHY_TYPE_USB3: case PHY_TYPE_PCIE: u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; - u3_banks->chip = NULL; + u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; break; |