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| author | Xiaoguang Chen <xiaoguang.chen@intel.com> | 2016-11-24 08:13:00 +0300 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2016-11-24 09:08:58 +0300 |
| commit | 550dd77ebb6360120269d9a7102ae2c0cea41290 (patch) | |
| tree | 1e8dd484023b881537acfc948376c459af4a21ef | |
| parent | e992faee1f82cebf39c65b340d7591ab1aa8c742 (diff) | |
| download | linux-550dd77ebb6360120269d9a7102ae2c0cea41290.tar.xz | |
drm/i915/gvt: fix getting 64bit bar size error
For 64bit bar while reading the higher 32bit the value should be returned
directly.
In the current implementation the higher 32bit value was discarded and not
written to the cfg space of vgpu which lead to an incorrect bar size.
Signed-off-by: Xiaoguang Chen <xiaoguang.chen@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/gvt.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 3d4223e8ebe3..b1a7c8dd4b5f 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -361,6 +361,8 @@ static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, * leave the bit 3 - bit 0 unchanged. */ *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); + } else { + *pval = val; } } |