diff options
| author | Torin Cooper-Bennun <torin@maxiluxsystems.com> | 2021-05-04 15:51:23 +0300 |
|---|---|---|
| committer | Marc Kleine-Budde <mkl@pengutronix.de> | 2021-05-27 10:42:24 +0300 |
| commit | 50fe7547b637b3cf51876ce9ec829e79d76e5de0 (patch) | |
| tree | 05c70e4c1e84f7c3df72075ab305806f9d3fa9ec | |
| parent | 0f31571668914f421dab628c45eeb391aaa127ef (diff) | |
| download | linux-50fe7547b637b3cf51876ce9ec829e79d76e5de0.tar.xz | |
can: m_can: fix whitespace in a few comments
Fixes whitespace in comments titling sections of register masks.
Link: https://lore.kernel.org/r/20210504125123.500553-5-torin@maxiluxsystems.com
Signed-off-by: Torin Cooper-Bennun <torin@maxiluxsystems.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
| -rw-r--r-- | drivers/net/can/m_can/m_can.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index ce7722229964..bba2a449ac70 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -101,7 +101,7 @@ enum m_can_reg { /* Test Register (TEST) */ #define TEST_LBCK BIT(4) -/* CC Control Register(CCCR) */ +/* CC Control Register (CCCR) */ #define CCCR_TXP BIT(14) #define CCCR_TEST BIT(7) #define CCCR_DAR BIT(6) @@ -147,18 +147,18 @@ enum m_can_reg { /* Timestamp Counter Value Register (TSCV) */ #define TSCV_TSC_MASK GENMASK(15, 0) -/* Error Counter Register(ECR) */ +/* Error Counter Register (ECR) */ #define ECR_RP BIT(15) #define ECR_REC_MASK GENMASK(14, 8) #define ECR_TEC_MASK GENMASK(7, 0) -/* Protocol Status Register(PSR) */ +/* Protocol Status Register (PSR) */ #define PSR_BO BIT(7) #define PSR_EW BIT(6) #define PSR_EP BIT(5) #define PSR_LEC_MASK GENMASK(2, 0) -/* Interrupt Register(IR) */ +/* Interrupt Register (IR) */ #define IR_ALL_INT 0xffffffff /* Renamed bits for versions > 3.1.x */ @@ -250,7 +250,7 @@ enum m_can_reg { #define TXFQS_TFGI_MASK GENMASK(12, 8) #define TXFQS_TFFL_MASK GENMASK(5, 0) -/* Tx Buffer Element Size Configuration(TXESC) */ +/* Tx Buffer Element Size Configuration (TXESC) */ #define TXESC_TBDS_MASK GENMASK(2, 0) #define TXESC_TBDS_64B 0x7 |