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authorMark Rutland <mark.rutland@arm.com>2015-07-01 15:36:01 +0300
committerKevin Hilman <khilman@linaro.org>2015-07-09 00:44:55 +0300
commit4d44f2a0266cdcc1226c7d94431ab1d57d0f6d53 (patch)
treecbb76688d63da313ef6c84ca4e87ddafe20d3ace
parentefc5120b8259243fa945d0028450c0a7a5a4b9ef (diff)
downloadlinux-4d44f2a0266cdcc1226c7d94431ab1d57d0f6d53.tar.xz
arm: dts: vexpress: describe all PMUs in TC2 dts
The dts for the CoreTile Express A15x2 A7x3 (TC2) only describes the PMUs of the Cortex-A15 CPUs, and not the Cortex-A7 CPUs. Now that we have a mechanism for describing disparate PMUs and their interrupts in device tree, this patch makes use of these to describe the PMUs for all CPUs in the system. For consistency, the existing A15 PMU interrupt-affinity property is reflowed across two lines. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts15
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 107395c32d82..038e30e4332f 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -187,11 +187,22 @@
<1 10 0xf08>;
};
- pmu {
+ pmu_a15 {
compatible = "arm,cortex-a15-pmu";
interrupts = <0 68 4>,
<0 69 4>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>;
+ };
+
+ pmu_a7 {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <0 128 4>,
+ <0 129 4>,
+ <0 130 4>;
+ interrupt-affinity = <&cpu2>,
+ <&cpu3>,
+ <&cpu4>;
};
oscclk6a: oscclk6a {