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| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2016-04-12 12:33:51 +0300 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2016-04-20 23:03:10 +0300 |
| commit | 12861674c99100b77dc78ed5037e4e1a5b95b0d5 (patch) | |
| tree | 25a6584f95b6eebc8bb54d101a669e2a3da9f70d | |
| parent | 67b5ad57df3537aa479010af1581e8c4edf580e4 (diff) | |
| download | linux-12861674c99100b77dc78ed5037e4e1a5b95b0d5.tar.xz | |
ARM: dts: apq8064: add support to gsbi1 uart
This patch adds support to gsbi1 uart and its pinctrls nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 14 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom-apq8064.dtsi | 10 |
2 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi index b57c59d5bc00..8bb5e5f3d07a 100644 --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi @@ -39,6 +39,20 @@ }; }; + gsbi1_uart_2pins: gsbi1_uart_2pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi1"; + }; + }; + + gsbi1_uart_4pins: gsbi1_uart_4pins { + mux { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "gsbi1"; + }; + }; + i2c2_pins: i2c2 { mux { pins = "gpio24", "gpio25"; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 18637c06566c..407a072dea69 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -319,6 +319,16 @@ syscon-tcsr = <&tcsr>; + gsbi1_serial: serial@12450000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12450000 0x100>, + <0x12400000 0x03>; + interrupts = <0 193 0x0>; + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + gsbi1_i2c: i2c@12460000 { compatible = "qcom,i2c-qup-v1.1.1"; pinctrl-0 = <&i2c1_pins>; |