diff options
| author | Emil Renner Berthing <kernel@esmil.dk> | 2021-11-20 19:13:22 +0300 |
|---|---|---|
| committer | Jianlong Huang <jianlong.huang@starfivetech.com> | 2022-06-13 06:39:13 +0300 |
| commit | e59913fdca1b1235d7ba5b44beecaf9d82a4892b (patch) | |
| tree | 98ddbebc373ff4be73918f3881a8496195b00ffc | |
| parent | 9aaa39d11da79d9732487a69b5ea8e80f7fb652d (diff) | |
| download | linux-e59913fdca1b1235d7ba5b44beecaf9d82a4892b.tar.xz | |
RISC-V: Add StarFive JH7100 audio clock node
Add device tree node for the audio clocks on the StarFive JH7100 RISC-V
SoC.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
| -rwxr-xr-x[-rw-r--r--] | arch/riscv/boot/dts/starfive/jh7100.dtsi | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index a35167a3b70b..a49301fbff97 100644..100755 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -272,6 +272,16 @@ snps,axi-max-burst-len = <64>; }; + audclk: clock-controller@10480000 { + compatible = "starfive,jh7100-audclk"; + reg = <0x0 0x10480000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_AUDIO_SRC>, + <&clkgen JH7100_CLK_AUDIO_12288>, + <&clkgen JH7100_CLK_DOM7AHB_BUS>; + clock-names = "audio_src", "audio_12288", "dom7ahb_bus"; + #clock-cells = <1>; + }; + clkgen: clock-controller@11800000 { compatible = "starfive,jh7100-clkgen"; reg = <0x0 0x11800000 0x0 0x10000>; @@ -757,16 +767,6 @@ dma-names = "tx"; }; - audclk: clock-controller@10480000 { - compatible = "starfive,jh7100-audclk"; - reg = <0x0 0x10480000 0x0 0x10000>; - clocks = <&clkgen JH7100_CLK_AUDIO_SRC>, - <&clkgen JH7100_CLK_AUDIO_12288>, - <&clkgen JH7100_CLK_DOM7AHB_BUS>; - clock-names = "audio_src", "audio_12288", "dom7ahb_bus"; - #clock-cells = <1>; - }; - audrst: reset-controller@10490000 { compatible = "starfive,jh7100-audrst"; reg = <0x0 0x10490000 0x0 0x10000>; |