drm: fixed coding style

Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>

17 files changed, 2557 insertions, 2591 deletions

diff --git a/drivers/gpu/drm/starfive/Makefile b/drivers/gpu/drm/starfive/Makefile
index e923d3985901..a71497dc71e7 100755
--- a/drivers/gpu/drm/starfive/Makefile
+++ b/drivers/gpu/drm/starfive/Makefile
@@ -1,14 +1,14 @@
-# SPDX-License-Identifier: GPL-2.0

-

-starfive-drm-y := starfive_drm_drv.o \

-		  starfive_drm_gem.o \

-		  starfive_drm_crtc.o \

-		  starfive_drm_encoder.o \

-		  starfive_drm_plane.o \

-		  starfive_drm_lcdc.o \

-		  starfive_drm_vpp.o \

-		  starfive_drm_dsi.o \

-		  starfive_drm_seeedpanel.o

-

-

-obj-$(CONFIG_DRM_STARFIVE) += starfive-drm.o

+# SPDX-License-Identifier: GPL-2.0
+
+starfive-drm-y := starfive_drm_drv.o \
+		  starfive_drm_gem.o \
+		  starfive_drm_crtc.o \
+		  starfive_drm_encoder.o \
+		  starfive_drm_plane.o \
+		  starfive_drm_lcdc.o \
+		  starfive_drm_vpp.o \
+		  starfive_drm_dsi.o \
+		  starfive_drm_seeedpanel.o
+
+
+obj-$(CONFIG_DRM_STARFIVE) += starfive-drm.o
diff --git a/drivers/gpu/drm/starfive/starfive_drm_crtc.c b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
index f198bc69fc9a..ebf01099bff1 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_crtc.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
@@ -1,535 +1,539 @@
-// SPDX-License-Identifier: GPL-2.0-only

-/*

- * Copyright (c) 2021 StarFive Technology Co., Ltd

- */

-

-#include <linux/clk.h>

-#include <linux/component.h>

-#include <linux/of_device.h>

-#include <linux/delay.h>

-

-#include <drm/drm_atomic.h>

-#include <drm/drm_atomic_helper.h>

-#include <drm/drm_atomic_uapi.h>

-#include <drm/drm_fb_cma_helper.h>

-#include <drm/drm_print.h>

-#include <drm/drm_probe_helper.h>

-#include <drm/drm_vblank.h>

-

-#include "starfive_drm_drv.h"

-#include "starfive_drm_crtc.h"

-#include "starfive_drm_plane.h"

-#include "starfive_drm_lcdc.h"

-#include "starfive_drm_vpp.h"

-

-struct resource_name {

-	char name[10];

-};

-

-static const struct resource_name mem_res_name[] = {

-	{"lcdc"},

-	{"vpp0"},

-	{"vpp1"},

-	{"vpp2"},

-	{"clk"},

-	{"rst"},

-	{"sys"}

-};

-

-static inline struct drm_encoder *

-starfive_head_atom_get_encoder(struct starfive_crtc *sf_crtc)

-{

-	struct drm_encoder *encoder = NULL;

-

-	/* We only ever have a single encoder */

-	drm_for_each_encoder_mask(encoder, sf_crtc->crtc.dev,

-				  sf_crtc->crtc.state->encoder_mask)

-		break;

-	return encoder;

-}

-

-static int ddrfmt_to_ppfmt(struct starfive_crtc *sf_crtc)

-{

-	int ddrfmt = sf_crtc->ddr_format;

-    int ret = 0;

-

-	sf_crtc->lcdcfmt = WIN_FMT_xRGB8888;//lcdc default used

-	sf_crtc->pp_conn_lcdc = 1;//default config

-	switch(ddrfmt)

-    {

-        case DRM_FORMAT_UYVY:

-            sf_crtc->vpp_format = COLOR_YUV422_UYVY;

-            break;

-        case DRM_FORMAT_VYUY:

-            sf_crtc->vpp_format = COLOR_YUV422_VYUY;

-            break;

-        case DRM_FORMAT_YUYV:

-            sf_crtc->vpp_format = COLOR_YUV422_YUYV;

-            break;

-        case DRM_FORMAT_YVYU:

-            sf_crtc->vpp_format = COLOR_YUV422_YVYU;

-            break;

-        case DRM_FORMAT_YUV420:

-            sf_crtc->vpp_format = COLOR_YUV420P;

-            break;

-        case DRM_FORMAT_NV21:

-            sf_crtc->vpp_format = COLOR_YUV420_NV21;

-            break;

-        case DRM_FORMAT_NV12:

-            sf_crtc->vpp_format = COLOR_YUV420_NV12;

-            break;

-        case DRM_FORMAT_ARGB8888:

-            sf_crtc->vpp_format = COLOR_RGB888_ARGB;

-            break;

-        case DRM_FORMAT_ABGR8888:

-            sf_crtc->vpp_format = COLOR_RGB888_ABGR;

-            break;

-        case DRM_FORMAT_RGBA8888:

-            sf_crtc->vpp_format = COLOR_RGB888_RGBA;

-            break;

-        case DRM_FORMAT_BGRA8888:

-            sf_crtc->vpp_format = COLOR_RGB888_BGRA;

-            break;

-        case DRM_FORMAT_RGB565:

-            sf_crtc->vpp_format = COLOR_RGB565;

-			//sf_crtc->lcdcfmt = WIN_FMT_RGB565;

-			//sf_crtc->pp_conn_lcdc = -1;//this format no need pp ,lcdc can direct read ddr buff;

-            break;

-		case DRM_FORMAT_XRGB1555:

-			sf_crtc->lcdcfmt = WIN_FMT_xRGB1555;

-			sf_crtc->pp_conn_lcdc = -1;//this format no need pp ,lcdc can direct read ddr buff;

-			break;

-		case DRM_FORMAT_XRGB4444:

-			sf_crtc->lcdcfmt = WIN_FMT_xRGB4444;

-			sf_crtc->pp_conn_lcdc = -1;//this format no need pp ,lcdc can direct read ddr buff;

-			break;

-

-		default:

-			ret = -1;

-		break;

-    }

-

-	return ret;

-}

-

-

-void starfive_crtc_hw_config_simple(struct starfive_crtc *starfive_crtc)

-{

-}

-

-static void starfive_crtc_destroy(struct drm_crtc *crtc)

-{

-	drm_crtc_cleanup(crtc);

-}

-

-static void starfive_crtc_destroy_state(struct drm_crtc *crtc,

-				   struct drm_crtc_state *state)

-{

-	struct starfive_crtc_state *s = to_starfive_crtc_state(state);

-

-	__drm_atomic_helper_crtc_destroy_state(&s->base);

-	kfree(s);

-}

-

-static void starfive_crtc_reset(struct drm_crtc *crtc)

-{

-	struct starfive_crtc_state *crtc_state =

-		kzalloc(sizeof(*crtc_state), GFP_KERNEL);

-

-	if (crtc->state)

-		starfive_crtc_destroy_state(crtc, crtc->state);

-

-	__drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);

-}

-

-static struct drm_crtc_state *starfive_crtc_duplicate_state(struct drm_crtc *crtc)

-{

-	struct starfive_crtc_state *starfive_state;

-

-	starfive_state = kzalloc(sizeof(*starfive_state), GFP_KERNEL);

-	if (!starfive_state)

-		return NULL;

-

-	__drm_atomic_helper_crtc_duplicate_state(crtc, &starfive_state->base);

-	return &starfive_state->base;

-}

-

-static int starfive_crtc_enable_vblank(struct drm_crtc *crtc)

-{

-	//need set hw

-	return 0;

-}

-

-static void starfive_crtc_disable_vblank(struct drm_crtc *crtc)

-{

-	//need set hw

-}

-

-

-

-static const struct drm_crtc_funcs starfive_crtc_funcs = {

-	.set_config = drm_atomic_helper_set_config,

-	.page_flip = drm_atomic_helper_page_flip,

-	.destroy = starfive_crtc_destroy,

-	.set_property = NULL, //vc

-	.cursor_set = NULL, /* handled by drm_mode_cursor_universal */ //vc

-	.cursor_move = NULL, /* handled by drm_mode_cursor_universal */ //vc

-	.reset = starfive_crtc_reset,

-	.atomic_duplicate_state = starfive_crtc_duplicate_state,

-	.atomic_destroy_state = starfive_crtc_destroy_state,

-	.gamma_set = drm_atomic_helper_legacy_gamma_set,

-	.enable_vblank = starfive_crtc_enable_vblank,

-	.disable_vblank = starfive_crtc_disable_vblank,

-	//.set_crc_source = starfive_crtc_set_crc_source, //rk

-	//.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, //vc

-	//.verify_crc_source = starfive_crtc_verify_crc_source,	//rk

-};

-

-

-static bool starfive_crtc_mode_fixup(struct drm_crtc *crtc,

-					const struct drm_display_mode *mode,

-					struct drm_display_mode *adjusted_mode)

-{

-	/* Nothing to do here, but this callback is mandatory. */

-	return true;

-}

-

-static int starfive_crtc_atomic_check(struct drm_crtc *crtc,

-				 struct drm_crtc_state *state)

-{

-	state->no_vblank = true;	// hardware without VBLANK interrupt ???

-	return 0;

-}

-

-static void starfive_crtc_atomic_begin(struct drm_crtc *crtc,

-				struct drm_crtc_state *old_crtc_state)

-{

-	//starfive_crtc_gamma_set(crtcp, crtc, old_crtc_state);

-}

-

-static void starfive_crtc_atomic_flush(struct drm_crtc *crtc,

-				  struct drm_crtc_state *old_crtc_state)

-{

-	struct starfive_crtc *crtcp = to_starfive_crtc(crtc);

-	DRM_DEBUG("ddr_format_change [%d],dma_addr_change [%d]\n",crtcp->ddr_format_change,crtcp->dma_addr_change);

-	int ret;

-

-	if((crtcp->ddr_format_change == true)||(crtcp->dma_addr_change == true))

-	{

-		ret = ddrfmt_to_ppfmt(crtcp);

-		starfive_pp_update(crtcp);

-		starfive_lcdc_enable(crtcp);

-	}

-	else

-		DRM_DEBUG("starfive_crtc_atomic_flush with no change\n");

-

-}

-

-static void starfive_crtc_atomic_enable(struct drm_crtc *crtc,

-				 struct drm_crtc_state *old_state)

-{

-	struct starfive_crtc *crtcp = to_starfive_crtc(crtc);

-	struct drm_crtc_state *state = crtc->state;

-	struct drm_encoder *encoder = NULL;

-	struct drm_device *drm = crtc->dev;

-	int ret;

-	encoder = starfive_head_atom_get_encoder(crtcp);

-

-	// enable crtc HW

-	if (encoder->encoder_type == DRM_MODE_ENCODER_DSI) {

-		printk("-----%s: %d\n", __func__, __LINE__);

-		dsitx_vout_init(crtcp);

-		lcdc_dsi_sel(crtcp);

-	} else if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) {

-		printk("-----%s: %d\n", __func__, __LINE__);

-		vout_reset(crtcp);

-	}

-

-	crtcp->encoder_type = encoder->encoder_type;

-    ret = ddrfmt_to_ppfmt(crtcp);

-	starfive_pp_enable(crtcp);

-	starfive_lcdc_enable(crtcp);

-	crtcp->is_enabled = true;  // should before

-}

-

-static void starfive_crtc_atomic_disable(struct drm_crtc *crtc,

-				 struct drm_crtc_state *old_state)

-{

-	struct starfive_crtc *crtcp = to_starfive_crtc(crtc);

-

-	int pp_id;

-	int ret = 0;

-	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {

-		if(1 == crtcp->pp[pp_id].inited) {

-			pp_disable_intr(crtcp, pp_id);

-			vout_disable(crtcp);// disable crtc HW

-		}

-	}

-	crtcp->is_enabled = false;

-}

-

-static enum drm_mode_status starfive_crtc_mode_valid(struct drm_crtc *crtc,

-						 const struct drm_display_mode *mode)

-{

-	int refresh = drm_mode_vrefresh(mode);

-	if(refresh > 60)//lcdc miss support 60+ fps

-		return MODE_BAD;

-	else

-		return MODE_OK;

-}

-

-static const struct drm_crtc_helper_funcs starfive_crtc_helper_funcs = {

-	//different inst in different platform

-	.mode_fixup = starfive_crtc_mode_fixup, //rk&mtk

-	.atomic_check = starfive_crtc_atomic_check, //mtk no

-	.atomic_begin = starfive_crtc_atomic_begin, //vc4 no

-	.atomic_flush = starfive_crtc_atomic_flush,

-	.atomic_enable = starfive_crtc_atomic_enable,

-	.atomic_disable = starfive_crtc_atomic_disable,

-	.mode_valid = starfive_crtc_mode_valid,

-	//.get_scanout_position = starfive_crtc_get_scanout_position, //vc

-};

-

-int starfive_crtc_create(struct drm_device *drm_dev, struct starfive_crtc *starfive_crtc,

-				  const struct drm_crtc_funcs *crtc_funcs,

-				  const struct drm_crtc_helper_funcs *crtc_helper_funcs)

-{

-	struct drm_crtc *crtc = &starfive_crtc->crtc;

-	struct device *dev = drm_dev->dev;

-	struct device_node *port;

-	//struct drm_plane *primary_plane;

-	int ret;

-

-	starfive_crtc->planes = devm_kzalloc(dev, sizeof(struct drm_plane), GFP_KERNEL);

-

-	ret = starfive_plane_init(drm_dev, starfive_crtc, DRM_PLANE_TYPE_PRIMARY);

-	if (ret) {

-		dev_err(drm_dev->dev, "failed to construct primary plane\n");

-		return ret;

-	}

-

-	drm_crtc_init_with_planes(drm_dev, crtc, starfive_crtc->planes, NULL,

-				  crtc_funcs, NULL);

-	drm_crtc_helper_add(crtc, crtc_helper_funcs);

-

-	port = of_get_child_by_name(starfive_crtc->dev->of_node, "port");

-	if (!port) {

-		DRM_ERROR("no port node found in %s\n",

-			  dev->of_node->full_name);

-		ret = -ENOENT;

-	}

-

-	crtc->port = port;

-

-	return 0;

-}

-

-static int starfive_crtc_get_memres(struct platform_device *pdev, struct starfive_crtc *sf_crtc)

-{

-  struct device *dev = &pdev->dev;

-  struct resource *res;

-  void __iomem *regs;

-  char *name;

-  int i;

-

-  for (i = 0; i < sizeof(mem_res_name)/sizeof(struct resource_name); i++) {

-	  name = (char *)(& mem_res_name[i]);

-	  res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);

-	  regs = devm_ioremap_resource(dev, res);

-	  if (IS_ERR(regs))

-		  return PTR_ERR(regs);

-

-	  if(!strcmp(name, "lcdc")) {

-		  sf_crtc->base_lcdc = regs;

-	  } else if (!strcmp(name, "vpp0")) {

-		  sf_crtc->base_vpp0 = regs;

-	  } else if (!strcmp(name, "vpp1")) {

-		  sf_crtc->base_vpp1 = regs;

-	  } else if (!strcmp(name, "vpp2")) {

-		  sf_crtc->base_vpp2 = regs;

-	  } else if (!strcmp(name, "clk")) {

-		  sf_crtc->base_clk = regs;

-	  } else if (!strcmp(name, "rst")) {

-		  sf_crtc->base_rst = regs;

-	  } else if (!strcmp(name, "sys")) {

-		  sf_crtc->base_syscfg = regs;

-	  } else {

-		  dev_err(&pdev->dev, "Could not match resource name\n");

-	  }

-  }

-

-  sf_crtc->topclk= ioremap(0x11800000, 0x10000);

-  sf_crtc->toprst= ioremap(0x11840000, 0x10000);

-

-  return 0;

-}

-

-static int starfive_parse_dt(struct device *dev, struct starfive_crtc *sf_crtc) {

-	int ret;

-	struct device_node *np = dev->of_node;

-	struct device_node *child;

-	int pp_num = 0;

-

-	if(!np)

-		return -EINVAL;

-

-	sf_crtc->pp = devm_kzalloc(dev, sizeof(struct pp_mode) * PP_NUM, GFP_KERNEL);

-	if (!sf_crtc->pp) {

-		dev_err(dev,"allocate memory for platform data failed\n");

-		return -ENOMEM;

-	}

-

-	for_each_child_of_node(np, child) {

-		if (of_property_read_u32(child, "pp-id", &pp_num)) {

-			ret = -EINVAL;

-			continue;

-		}

-		if (pp_num >= PP_NUM)

-			dev_err(dev," pp-id number %d is not support!\n", pp_num);

-

-		sf_crtc->pp[pp_num].pp_id = pp_num;

-		sf_crtc->pp[pp_num].bus_out = of_property_read_bool(child, "sys-bus-out");

-		sf_crtc->pp[pp_num].fifo_out = of_property_read_bool(child, "fifo-out");

-		if (of_property_read_u32(child, "src-format", &sf_crtc->pp[pp_num].src.format)) {

-			dev_err(dev,"Missing src-format property in the DT.\n");

-			ret = -EINVAL;

-		}

-		if (of_property_read_u32(child, "src-width", &sf_crtc->pp[pp_num].src.width)) {

-			dev_err(dev,"Missing src-width property in the DT. w %d \n", sf_crtc->pp[pp_num].src.width);

-			ret = -EINVAL;

-		}

-		if (of_property_read_u32(child, "src-height", &sf_crtc->pp[pp_num].src.height)) {

-			dev_err(dev,"Missing src-height property in the DT.\n");

-			ret = -EINVAL;

-		}

-		if (of_property_read_u32(child, "dst-format", &sf_crtc->pp[pp_num].dst.format)) {

-			dev_err(dev,"Missing dst-format property in the DT.\n");

-			ret = -EINVAL;

-		}

-		if (of_property_read_u32(child, "dst-width", &sf_crtc->pp[pp_num].dst.width)) {

-			dev_err(dev,"Missing dst-width property in the DT.\n");

-			ret = -EINVAL;

-		}

-		if (of_property_read_u32(child, "dst-height", &sf_crtc->pp[pp_num].dst.height)) {

-			dev_err(dev,"Missing dst-height property in the DT.\n");

-			ret = -EINVAL;

-		}

-

-		sf_crtc->pp[pp_num].inited = 1;

-	}

-

-	return ret;

-}

-

-static int starfive_crtc_bind(struct device *dev, struct device *master, void *data)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	struct platform_device *pdev = to_platform_device(dev);

-	struct drm_device *drm_dev = data;

-	struct starfive_crtc *crtcp;

-	struct device_node *np = dev->of_node;

-	int ret;

-

-	crtcp = devm_kzalloc(dev, sizeof(*crtcp), GFP_KERNEL);

-	if (!crtcp)

-		return -ENOMEM;

-

-	crtcp->dev = dev;

-	crtcp->drm_dev = drm_dev;

-	dev_set_drvdata(dev, crtcp);

-

-	spin_lock_init(&crtcp->reg_lock);

-

-	starfive_crtc_get_memres(pdev, crtcp);

-	ret = starfive_parse_dt(dev, crtcp);

-

-	crtcp->pp_conn_lcdc = starfive_pp_get_2lcdc_id(crtcp);

-

-	crtcp->lcdc_irq = platform_get_irq_byname(pdev, "lcdc_irq");

-	if (crtcp->lcdc_irq == -EPROBE_DEFER)

-		return crtcp->lcdc_irq;

-	if (crtcp->lcdc_irq < 0) {

-		dev_err(dev, "couldn't get lcdc irq\n");

-		return crtcp->lcdc_irq;

-	}

-

-	crtcp->vpp1_irq = platform_get_irq_byname(pdev, "vpp1_irq");

-	if (crtcp->vpp1_irq == -EPROBE_DEFER)

-		return crtcp->vpp1_irq;

-	if (crtcp->vpp1_irq < 0) {

-		dev_err(dev, "couldn't get vpp1 irq\n");

-		return crtcp->vpp1_irq;

-	}

-

-	ret = devm_request_irq(&pdev->dev, crtcp->lcdc_irq, lcdc_isr_handler, 0,

-				   "sf_lcdc", crtcp);

-	if (ret) {

-		dev_err(&pdev->dev, "failure requesting irq %i: %d\n",

-			crtcp->lcdc_irq, ret);

-		return ret;

-	}

-

-

-	ret = devm_request_irq(&pdev->dev, crtcp->vpp1_irq, vpp1_isr_handler, 0,

-			       "sf_vpp1", crtcp);

-	if (ret) {

-		dev_err(&pdev->dev, "failure requesting irq %i: %d\n",

-			crtcp->vpp1_irq, ret);

-		return ret;

-	}

-

-	ret = starfive_crtc_create(drm_dev, crtcp,

-			    &starfive_crtc_funcs, &starfive_crtc_helper_funcs);

-	if (ret)

-		return ret;

-

-	crtcp->is_enabled = false;

-

-	return 0;

-}

-

-static void starfive_crtc_unbind(struct device *dev, struct device *master, void *data)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	struct platform_device *pdev = to_platform_device(dev);

-	struct starfive_crtc *crtcp = dev_get_drvdata(dev);

-

-	vout_disable(crtcp);// disable crtc HW

-

-	crtcp->is_enabled = false;

-}

-

-

-static const struct component_ops starfive_crtc_component_ops = {

-	.bind   = starfive_crtc_bind,

-	.unbind = starfive_crtc_unbind,

-};

-

-static const struct of_device_id starfive_crtc_driver_dt_match[] = {

-	{ .compatible = "starfive,jh7100-crtc",

-	  /*.data = &7100-crtc*/ },

-	{},

-};

-MODULE_DEVICE_TABLE(of, starfive_crtc_driver_dt_match);

-

-static int starfive_crtc_probe(struct platform_device *pdev)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	return component_add(&pdev->dev, &starfive_crtc_component_ops);

-}

-

-static int starfive_crtc_remove(struct platform_device *pdev)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	component_del(&pdev->dev, &starfive_crtc_component_ops);

-	return 0;

-}

-

-struct platform_driver starfive_crtc_driver = {

-	.probe = starfive_crtc_probe,

-	.remove = starfive_crtc_remove,

-	.driver = {

-		.name = "starfive-crtc",

-		.of_match_table = of_match_ptr(starfive_crtc_driver_dt_match),

-	},

-};

+//SPDX-License-Identifier:GPL-2.0-only
+/*
+ * Copyright (c) 2021 StarFive Technology Co., Ltd
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/delay.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic_uapi.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+
+#include "starfive_drm_drv.h"
+#include "starfive_drm_crtc.h"
+#include "starfive_drm_plane.h"
+#include "starfive_drm_lcdc.h"
+#include "starfive_drm_vpp.h"
+
+struct resource_name {
+	char name[10];
+};
+
+static const struct resource_name mem_res_name[] = {
+	{"lcdc"},
+	{"vpp0"},
+	{"vpp1"},
+	{"vpp2"},
+	{"clk"},
+	{"rst"},
+	{"sys"}
+};
+
+static inline struct drm_encoder *
+starfive_head_atom_get_encoder(struct starfive_crtc *sf_crtc)
+{
+	struct drm_encoder *encoder = NULL;
+
+	/* We only ever have a single encoder */
+	drm_for_each_encoder_mask(encoder, sf_crtc->crtc.dev,
+				  sf_crtc->crtc.state->encoder_mask)
+		break;
+	return encoder;
+}
+
+static int ddrfmt_to_ppfmt(struct starfive_crtc *sf_crtc)
+{
+	int ddrfmt = sf_crtc->ddr_format;
+	int ret = 0;
+
+	sf_crtc->lcdcfmt = WIN_FMT_xRGB8888;//lcdc default used
+	sf_crtc->pp_conn_lcdc = 1;//default config
+
+	switch (ddrfmt) {
+	case DRM_FORMAT_UYVY:
+		sf_crtc->vpp_format = COLOR_YUV422_UYVY;
+		break;
+	case DRM_FORMAT_VYUY:
+		sf_crtc->vpp_format = COLOR_YUV422_VYUY;
+		break;
+	case DRM_FORMAT_YUYV:
+		sf_crtc->vpp_format = COLOR_YUV422_YUYV;
+		break;
+	case DRM_FORMAT_YVYU:
+		sf_crtc->vpp_format = COLOR_YUV422_YVYU;
+		break;
+	case DRM_FORMAT_YUV420:
+		sf_crtc->vpp_format = COLOR_YUV420P;
+		break;
+	case DRM_FORMAT_NV21:
+		sf_crtc->vpp_format = COLOR_YUV420_NV21;
+		break;
+	case DRM_FORMAT_NV12:
+		sf_crtc->vpp_format = COLOR_YUV420_NV12;
+		break;
+	case DRM_FORMAT_ARGB8888:
+		sf_crtc->vpp_format = COLOR_RGB888_ARGB;
+		break;
+	case DRM_FORMAT_ABGR8888:
+		sf_crtc->vpp_format = COLOR_RGB888_ABGR;
+		break;
+	case DRM_FORMAT_RGBA8888:
+		sf_crtc->vpp_format = COLOR_RGB888_RGBA;
+		break;
+	case DRM_FORMAT_BGRA8888:
+		sf_crtc->vpp_format = COLOR_RGB888_BGRA;
+		break;
+	case DRM_FORMAT_RGB565:
+		sf_crtc->vpp_format = COLOR_RGB565;
+		//sf_crtc->lcdcfmt = WIN_FMT_RGB565;
+		/*this format no need pp,lcdc can direct read ddr buff*/
+		//sf_crtc->pp_conn_lcdc = -1;
+		break;
+	case DRM_FORMAT_XRGB1555:
+		sf_crtc->lcdcfmt = WIN_FMT_xRGB1555;
+		/*this format no need pp,lcdc can direct read ddr buff*/
+		sf_crtc->pp_conn_lcdc = -1;
+		break;
+	case DRM_FORMAT_XRGB4444:
+		sf_crtc->lcdcfmt = WIN_FMT_xRGB4444;
+		/*this format no need pp,lcdc can direct read ddr buff*/
+		sf_crtc->pp_conn_lcdc = -1;
+		break;
+
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
+
+
+void starfive_crtc_hw_config_simple(struct starfive_crtc *starfive_crtc)
+{
+}
+
+static void starfive_crtc_destroy(struct drm_crtc *crtc)
+{
+	drm_crtc_cleanup(crtc);
+}
+
+static void starfive_crtc_destroy_state(struct drm_crtc *crtc,
+				   struct drm_crtc_state *state)
+{
+	struct starfive_crtc_state *s = to_starfive_crtc_state(state);
+
+	__drm_atomic_helper_crtc_destroy_state(&s->base);
+	kfree(s);
+}
+
+static void starfive_crtc_reset(struct drm_crtc *crtc)
+{
+	struct starfive_crtc_state *crtc_state =
+		kzalloc(sizeof(*crtc_state), GFP_KERNEL);
+
+	if (crtc->state)
+		starfive_crtc_destroy_state(crtc, crtc->state);
+
+	__drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
+}
+
+static struct drm_crtc_state *
+starfive_crtc_duplicate_state(struct drm_crtc *crtc)
+{
+	struct starfive_crtc_state *starfive_state;
+
+	starfive_state = kzalloc(sizeof(*starfive_state), GFP_KERNEL);
+	if (!starfive_state)
+		return NULL;
+
+	__drm_atomic_helper_crtc_duplicate_state(crtc, &starfive_state->base);
+	return &starfive_state->base;
+}
+
+static int starfive_crtc_enable_vblank(struct drm_crtc *crtc)
+{
+	//need set hw
+	return 0;
+}
+
+static void starfive_crtc_disable_vblank(struct drm_crtc *crtc)
+{
+	//need set hw
+}
+
+static const struct drm_crtc_funcs starfive_crtc_funcs = {
+	.set_config = drm_atomic_helper_set_config,
+	.page_flip = drm_atomic_helper_page_flip,
+	.destroy = starfive_crtc_destroy,
+	.set_property = NULL, //vc
+	.cursor_set = NULL, /* handled by drm_mode_cursor_universal */
+	.cursor_move = NULL, /* handled by drm_mode_cursor_universal */
+	.reset = starfive_crtc_reset,
+	.atomic_duplicate_state = starfive_crtc_duplicate_state,
+	.atomic_destroy_state = starfive_crtc_destroy_state,
+	.gamma_set = drm_atomic_helper_legacy_gamma_set,
+	.enable_vblank = starfive_crtc_enable_vblank,
+	.disable_vblank = starfive_crtc_disable_vblank,
+	//.set_crc_source = starfive_crtc_set_crc_source, //rk
+	//.get_vblank_timestamp =
+	//drm_crtc_vblank_helper_get_vblank_timestamp, //vc
+	//.verify_crc_source = starfive_crtc_verify_crc_source,	//rk
+};
+
+
+static bool starfive_crtc_mode_fixup(struct drm_crtc *crtc,
+					const struct drm_display_mode *mode,
+					struct drm_display_mode *adjusted_mode)
+{
+	/* Nothing to do here, but this callback is mandatory. */
+	return true;
+}
+
+static int starfive_crtc_atomic_check(struct drm_crtc *crtc,
+				 struct drm_crtc_state *state)
+{
+	state->no_vblank = true;	// hardware without VBLANK interrupt ???
+	return 0;
+}
+
+static void starfive_crtc_atomic_begin(struct drm_crtc *crtc,
+				struct drm_crtc_state *old_crtc_state)
+{
+	//starfive_crtc_gamma_set(crtcp, crtc, old_crtc_state);
+}
+
+static void starfive_crtc_atomic_flush(struct drm_crtc *crtc,
+				  struct drm_crtc_state *old_crtc_state)
+{
+	struct starfive_crtc *crtcp = to_starfive_crtc(crtc);
+
+	DRM_DEBUG("ddr_format_change [%d],dma_addr_change [%d]\n",
+		crtcp->ddr_format_change, crtcp->dma_addr_change);
+	int ret;
+
+	if (crtcp->ddr_format_change || crtcp->dma_addr_change) {
+		ret = ddrfmt_to_ppfmt(crtcp);
+		starfive_pp_update(crtcp);
+		starfive_lcdc_enable(crtcp);
+	} else
+		DRM_DEBUG("%s with no change\n", __func__);
+}
+
+static void starfive_crtc_atomic_enable(struct drm_crtc *crtc,
+				 struct drm_crtc_state *old_state)
+{
+	struct starfive_crtc *crtcp = to_starfive_crtc(crtc);
+	struct drm_crtc_state *state = crtc->state;
+	struct drm_encoder *encoder = NULL;
+	struct drm_device *drm = crtc->dev;
+
+	encoder = starfive_head_atom_get_encoder(crtcp);
+
+	// enable crtc HW
+	if (encoder->encoder_type == DRM_MODE_ENCODER_DSI) {
+		dsitx_vout_init(crtcp);
+		lcdc_dsi_sel(crtcp);
+	} else if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
+		vout_reset(crtcp);
+
+	crtcp->encoder_type = encoder->encoder_type;
+
+    ddrfmt_to_ppfmt(crtcp);
+	starfive_pp_enable(crtcp);
+	starfive_lcdc_enable(crtcp);
+	crtcp->is_enabled = true;  // should before
+}
+
+static void starfive_crtc_atomic_disable(struct drm_crtc *crtc,
+				 struct drm_crtc_state *old_state)
+{
+	struct starfive_crtc *crtcp = to_starfive_crtc(crtc);
+
+	int pp_id;
+	int ret = 0;
+
+	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
+		if (crtcp->pp[pp_id].inited == 1) {
+			pp_disable_intr(crtcp, pp_id);
+			vout_disable(crtcp);// disable crtc HW
+		}
+	}
+	crtcp->is_enabled = false;
+}
+
+static enum drm_mode_status starfive_crtc_mode_valid(
+	struct drm_crtc *crtc,
+	const struct drm_display_mode *mode)
+{
+	int refresh = drm_mode_vrefresh(mode);
+
+	if (refresh > 60)//lcdc miss support 60+ fps
+		return MODE_BAD;
+	else
+		return MODE_OK;
+}
+
+static const struct drm_crtc_helper_funcs starfive_crtc_helper_funcs = {
+	//different inst in different platform
+	.mode_fixup = starfive_crtc_mode_fixup, //rk&mtk
+	.atomic_check = starfive_crtc_atomic_check, //mtk no
+	.atomic_begin = starfive_crtc_atomic_begin, //vc4 no
+	.atomic_flush = starfive_crtc_atomic_flush,
+	.atomic_enable = starfive_crtc_atomic_enable,
+	.atomic_disable = starfive_crtc_atomic_disable,
+	.mode_valid = starfive_crtc_mode_valid,
+	//.get_scanout_position = starfive_crtc_get_scanout_position, //vc
+};
+
+int starfive_crtc_create(struct drm_device *drm_dev,
+	struct starfive_crtc *starfive_crtc,
+	const struct drm_crtc_funcs *crtc_funcs,
+	const struct drm_crtc_helper_funcs *crtc_helper_funcs)
+{
+	struct drm_crtc *crtc = &starfive_crtc->crtc;
+	struct device *dev = drm_dev->dev;
+	struct device_node *port;
+	//struct drm_plane *primary_plane;
+	int ret;
+
+	starfive_crtc->planes = devm_kzalloc(dev, sizeof(struct drm_plane),
+										GFP_KERNEL);
+
+	ret = starfive_plane_init(drm_dev, starfive_crtc,
+					DRM_PLANE_TYPE_PRIMARY);
+	if (ret) {
+		dev_err(drm_dev->dev, "failed to construct primary plane\n");
+		return ret;
+	}
+
+	drm_crtc_init_with_planes(drm_dev, crtc, starfive_crtc->planes, NULL,
+				  crtc_funcs, NULL);
+	drm_crtc_helper_add(crtc, crtc_helper_funcs);
+
+	port = of_get_child_by_name(starfive_crtc->dev->of_node, "port");
+	if (!port) {
+		DRM_ERROR("no port node found in %s\n",
+			  dev->of_node->full_name);
+		ret = -ENOENT;
+	}
+
+	crtc->port = port;
+
+	return 0;
+}
+
+static int starfive_crtc_get_memres(struct platform_device *pdev,
+	struct starfive_crtc *sf_crtc)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	void __iomem *regs;
+	char *name;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(mem_res_name); i++) {
+		name = (char *)(&mem_res_name[i]);
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+		regs = devm_ioremap_resource(dev, res);
+		if (IS_ERR(regs))
+			return PTR_ERR(regs);
+
+		if (!strcmp(name, "lcdc"))
+			sf_crtc->base_lcdc = regs;
+		else if (!strcmp(name, "vpp0"))
+			sf_crtc->base_vpp0 = regs;
+		else if (!strcmp(name, "vpp1"))
+			sf_crtc->base_vpp1 = regs;
+		else if (!strcmp(name, "vpp2"))
+			sf_crtc->base_vpp2 = regs;
+		else if (!strcmp(name, "clk"))
+			sf_crtc->base_clk = regs;
+		else if (!strcmp(name, "rst"))
+			sf_crtc->base_rst = regs;
+		else if (!strcmp(name, "sys"))
+			sf_crtc->base_syscfg = regs;
+		else
+			dev_err(&pdev->dev, "Could not match resource name\n");
+	}
+
+	sf_crtc->topclk = ioremap(0x11800000, 0x10000);
+	sf_crtc->toprst = ioremap(0x11840000, 0x10000);
+
+	return 0;
+}
+
+static int starfive_parse_dt(struct device *dev,
+	struct starfive_crtc *sf_crtc)
+{
+	int ret;
+	struct device_node *np = dev->of_node;
+	struct device_node *child;
+	int pp_num = 0;
+
+	if (!np)
+		return -EINVAL;
+
+	sf_crtc->pp = devm_kzalloc(dev, sizeof(struct pp_mode) * PP_NUM, GFP_KERNEL);
+	if (!sf_crtc->pp)
+		return -ENOMEM;
+
+	for_each_child_of_node(np, child) {
+		if (of_property_read_u32(child, "pp-id", &pp_num)) {
+			ret = -EINVAL;
+			continue;
+		}
+		if (pp_num >= PP_NUM)
+			dev_err(dev, "pp-id number %d is not support!\n", pp_num);
+
+		sf_crtc->pp[pp_num].pp_id = pp_num;
+		sf_crtc->pp[pp_num].bus_out = of_property_read_bool(child, "sys-bus-out");
+		sf_crtc->pp[pp_num].fifo_out = of_property_read_bool(child, "fifo-out");
+		if (of_property_read_u32(child, "src-format", &sf_crtc->pp[pp_num].src.format)) {
+			dev_err(dev, "Missing src-format property in the DT.\n");
+			ret = -EINVAL;
+		}
+		if (of_property_read_u32(child, "src-width", &sf_crtc->pp[pp_num].src.width)) {
+			dev_err(dev, "Missing src-width property in the DT. w %d\n", sf_crtc->pp[pp_num].src.width);
+			ret = -EINVAL;
+		}
+		if (of_property_read_u32(child, "src-height", &sf_crtc->pp[pp_num].src.height)) {
+			dev_err(dev, "Missing src-height property in the DT.\n");
+			ret = -EINVAL;
+		}
+		if (of_property_read_u32(child, "dst-format", &sf_crtc->pp[pp_num].dst.format)) {
+			dev_err(dev, "Missing dst-format property in the DT.\n");
+			ret = -EINVAL;
+		}
+		if (of_property_read_u32(child, "dst-width", &sf_crtc->pp[pp_num].dst.width)) {
+			dev_err(dev, "Missing dst-width property in the DT.\n");
+			ret = -EINVAL;
+		}
+		if (of_property_read_u32(child, "dst-height", &sf_crtc->pp[pp_num].dst.height)) {
+			dev_err(dev, "Missing dst-height property in the DT.\n");
+			ret = -EINVAL;
+		}
+
+		sf_crtc->pp[pp_num].inited = 1;
+	}
+
+	return ret;
+}
+
+static int starfive_crtc_bind(struct device *dev, struct device *master, void *data)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	struct platform_device *pdev = to_platform_device(dev);
+	struct drm_device *drm_dev = data;
+	struct starfive_crtc *crtcp;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	crtcp = devm_kzalloc(dev, sizeof(*crtcp), GFP_KERNEL);
+	if (!crtcp)
+		return -ENOMEM;
+
+	crtcp->dev = dev;
+	crtcp->drm_dev = drm_dev;
+	dev_set_drvdata(dev, crtcp);
+
+	spin_lock_init(&crtcp->reg_lock);
+
+	starfive_crtc_get_memres(pdev, crtcp);
+	ret = starfive_parse_dt(dev, crtcp);
+
+	crtcp->pp_conn_lcdc = starfive_pp_get_2lcdc_id(crtcp);
+
+	crtcp->lcdc_irq = platform_get_irq_byname(pdev, "lcdc_irq");
+	if (crtcp->lcdc_irq == -EPROBE_DEFER)
+		return crtcp->lcdc_irq;
+	if (crtcp->lcdc_irq < 0) {
+		dev_err(dev, "couldn't get lcdc irq\n");
+		return crtcp->lcdc_irq;
+	}
+
+	crtcp->vpp1_irq = platform_get_irq_byname(pdev, "vpp1_irq");
+	if (crtcp->vpp1_irq == -EPROBE_DEFER)
+		return crtcp->vpp1_irq;
+	if (crtcp->vpp1_irq < 0) {
+		dev_err(dev, "couldn't get vpp1 irq\n");
+		return crtcp->vpp1_irq;
+	}
+
+	ret = devm_request_irq(&pdev->dev, crtcp->lcdc_irq, lcdc_isr_handler, 0,
+				   "sf_lcdc", crtcp);
+	if (ret) {
+		dev_err(&pdev->dev, "failure requesting irq %i: %d\n",
+			crtcp->lcdc_irq, ret);
+		return ret;
+	}
+
+
+	ret = devm_request_irq(&pdev->dev, crtcp->vpp1_irq, vpp1_isr_handler, 0,
+			       "sf_vpp1", crtcp);
+	if (ret) {
+		dev_err(&pdev->dev, "failure requesting irq %i: %d\n",
+			crtcp->vpp1_irq, ret);
+		return ret;
+	}
+
+	ret = starfive_crtc_create(drm_dev, crtcp,
+			    &starfive_crtc_funcs, &starfive_crtc_helper_funcs);
+	if (ret)
+		return ret;
+
+	crtcp->is_enabled = false;
+
+	return 0;
+}
+
+static void starfive_crtc_unbind(struct device *dev, struct device *master, void *data)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	struct platform_device *pdev = to_platform_device(dev);
+	struct starfive_crtc *crtcp = dev_get_drvdata(dev);
+
+	vout_disable(crtcp);// disable crtc HW
+
+	crtcp->is_enabled = false;
+}
+
+static const struct component_ops starfive_crtc_component_ops = {
+	.bind   = starfive_crtc_bind,
+	.unbind = starfive_crtc_unbind,
+};
+
+static const struct of_device_id starfive_crtc_driver_dt_match[] = {
+	{ .compatible = "starfive,jh7100-crtc",
+	  /*.data = &7100-crtc*/ },
+	{},
+};
+MODULE_DEVICE_TABLE(of, starfive_crtc_driver_dt_match);
+
+static int starfive_crtc_probe(struct platform_device *pdev)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	return component_add(&pdev->dev, &starfive_crtc_component_ops);
+}
+
+static int starfive_crtc_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &starfive_crtc_component_ops);
+	return 0;
+}
+
+struct platform_driver starfive_crtc_driver = {
+	.probe = starfive_crtc_probe,
+	.remove = starfive_crtc_remove,
+	.driver = {
+		.name = "starfive-crtc",
+		.of_match_table = of_match_ptr(starfive_crtc_driver_dt_match),
+	},
+};
diff --git a/drivers/gpu/drm/starfive/starfive_drm_crtc.h b/drivers/gpu/drm/starfive/starfive_drm_crtc.h
index ceae7ef89bef..91fd3077de0b 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_crtc.h
+++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.h
@@ -1,84 +1,84 @@
-/* SPDX-License-Identifier: GPL-2.0-only */

-/*

- * Copyright (c) 2021 StarFive Technology Co., Ltd

- * Author: StarFive <StarFive@starfivetech.com>

- */

-

-#ifndef _STARFIVE_DRM_CRTC_H

-#define _STARFIVE_DRM_CRTC_H

-#include <drm/drm_crtc.h>

-

-enum COLOR_FORMAT{

-    COLOR_YUV422_UYVY = 0,  //00={Y1,V0,Y0,U0}

-    COLOR_YUV422_VYUY = 1,  //01={Y1,U0,Y0,V0}

-    COLOR_YUV422_YUYV = 2,  //10={V0,Y1,U0,Y0}

-    COLOR_YUV422_YVYU = 3,  //11={U0,Y1,V0,Y0}

-

-    COLOR_YUV420P,

-    COLOR_YUV420_NV12,

-    COLOR_YUV420_NV21,

-

-    COLOR_RGB888_ARGB,

-    COLOR_RGB888_ABGR,

-    COLOR_RGB888_RGBA,

-    COLOR_RGB888_BGRA,

-    COLOR_RGB565,

-};

-

-

-struct starfive_crtc_state {

-	struct drm_crtc_state base;

-};

-#define to_starfive_crtc_state(s) \

-		container_of(s, struct starfive_crtc_state, base)

-

-struct starfive_crtc {

-	struct drm_crtc		crtc;

-	struct device		*dev;

-	struct drm_device	*drm_dev;

-	bool is_enabled;

-

-	void __iomem	*base_clk;    //0x12240000

-	void __iomem	*base_rst;    //0x12250000

-	void __iomem	*base_syscfg; //0x12260000

-	void __iomem	*base_vpp0;   //0x12040000

-	void __iomem	*base_vpp1;   //0x12080000

-	void __iomem	*base_vpp2;   //0x120c0000

-	void __iomem	*base_lcdc;   //0x12000000

-

-	void __iomem 	*topclk;      //(0x11800000, 0x10000);

-	void __iomem 	*toprst;      //(0x11840000, 0x10000);

-

-	int				lcdc_irq;

-	int 			vpp0_irq;

-	int 			vpp1_irq;

-	int 			vpp2_irq;

-

-	struct pp_mode *pp;

-

-	int winNum;

-	int pp_conn_lcdc;

-	unsigned int ddr_format;

-	bool ddr_format_change;

-	enum COLOR_FORMAT vpp_format;

-	int lcdcfmt;

-

-	/* one time only one process allowed to config the register */

-	spinlock_t	reg_lock;

-

-	struct drm_plane	*planes;

-

-	u8 lut_r[256];

-	u8 lut_g[256];

-	u8 lut_b[256];

-

-	bool		gamma_lut;

-	int         encoder_type;

-	dma_addr_t  dma_addr;

-	bool    	dma_addr_change;

-};

-#define to_starfive_crtc(x) container_of(x, struct starfive_crtc, crtc)

-

-void starfive_crtc_hw_config_simple(struct starfive_crtc *starfive_crtc);

-

-#endif /* _STARFIVE_DRM_CRTC_H */

+/* SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2021 StarFive Technology Co., Ltd
+ * Author: StarFive <StarFive@starfivetech.com>
+ */
+
+#ifndef _STARFIVE_DRM_CRTC_H
+#define _STARFIVE_DRM_CRTC_H
+#include <drm/drm_crtc.h>
+
+enum COLOR_FORMAT {
+	COLOR_YUV422_UYVY = 0,  //00={Y1,V0,Y0,U0}
+	COLOR_YUV422_VYUY = 1,  //01={Y1,U0,Y0,V0}
+	COLOR_YUV422_YUYV = 2,  //10={V0,Y1,U0,Y0}
+	COLOR_YUV422_YVYU = 3,  //11={U0,Y1,V0,Y0}
+
+	COLOR_YUV420P,
+	COLOR_YUV420_NV12,
+	COLOR_YUV420_NV21,
+
+	COLOR_RGB888_ARGB,
+	COLOR_RGB888_ABGR,
+	COLOR_RGB888_RGBA,
+	COLOR_RGB888_BGRA,
+	COLOR_RGB565,
+};
+
+
+struct starfive_crtc_state {
+	struct drm_crtc_state base;
+};
+#define to_starfive_crtc_state(s) \
+		container_of(s, struct starfive_crtc_state, base)
+
+struct starfive_crtc {
+	struct drm_crtc		crtc;
+	struct device		*dev;
+	struct drm_device	*drm_dev;
+	bool is_enabled;
+
+	void __iomem	*base_clk;    //0x12240000
+	void __iomem	*base_rst;    //0x12250000
+	void __iomem	*base_syscfg; //0x12260000
+	void __iomem	*base_vpp0;   //0x12040000
+	void __iomem	*base_vpp1;   //0x12080000
+	void __iomem	*base_vpp2;   //0x120c0000
+	void __iomem	*base_lcdc;   //0x12000000
+
+	void __iomem	*topclk;      //(0x11800000, 0x10000);
+	void __iomem	*toprst;      //(0x11840000, 0x10000);
+
+	int				lcdc_irq;
+	int				vpp0_irq;
+	int				vpp1_irq;
+	int				vpp2_irq;
+
+	struct pp_mode *pp;
+
+	int winNum;
+	int pp_conn_lcdc;
+	unsigned int ddr_format;
+	bool ddr_format_change;
+	enum COLOR_FORMAT vpp_format;
+	int lcdcfmt;
+
+	/* one time only one process allowed to config the register */
+	spinlock_t	reg_lock;
+
+	struct drm_plane	*planes;
+
+	u8 lut_r[256];
+	u8 lut_g[256];
+	u8 lut_b[256];
+
+	bool		gamma_lut;
+	int			encoder_type;
+	dma_addr_t	dma_addr;
+	bool		dma_addr_change;
+};
+#define to_starfive_crtc(x) container_of(x, struct starfive_crtc, crtc)
+
+void starfive_crtc_hw_config_simple(struct starfive_crtc *starfive_crtc);
+
+#endif /* _STARFIVE_DRM_CRTC_H */
diff --git a/drivers/gpu/drm/starfive/starfive_drm_drv.c b/drivers/gpu/drm/starfive/starfive_drm_drv.c
index 959ca6bcd55b..1e6653195b9c 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_drv.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_drv.c
@@ -1,280 +1,280 @@
-// SPDX-License-Identifier: GPL-2.0-only

-/*

- * Copyright (c) 2021 StarFive Technology Co., Ltd

- * Author: StarFive <StarFive@starfivetech.com>

- */

-

-#include <linux/component.h>

-#include <linux/iommu.h>

-#include <linux/module.h>

-#include <linux/of_address.h>

-#include <linux/of_platform.h>

-#include <linux/pm_runtime.h>

-#include <linux/soc/mediatek/mtk-mmsys.h>

-#include <linux/dma-mapping.h>

-#include <drm/drm_atomic.h>

-#include <drm/drm_atomic_helper.h>

-#include <drm/drm_drv.h>

-#include <drm/drm_fb_helper.h>

-#include <drm/drm_fourcc.h>

-#include <drm/drm_gem.h>

-#include <drm/drm_gem_cma_helper.h>

-#include <drm/drm_gem_framebuffer_helper.h>

-#include <drm/drm_of.h>

-#include <drm/drm_probe_helper.h>

-#include <drm/drm_vblank.h>

-#include "starfive_drm_drv.h"

-#include "starfive_drm_gem.h"

-

-#define DRIVER_NAME	"starfive"

-#define DRIVER_DESC	"starfive Soc DRM"

-#define DRIVER_DATE	"20210519"

-#define DRIVER_MAJOR	1

-#define DRIVER_MINOR	0

-

-static struct drm_framebuffer *

-starfive_drm_mode_fb_create(struct drm_device *dev, struct drm_file *file,

-		   const struct drm_mode_fb_cmd2 *mode_cmd)

-{

-	const struct drm_format_info *info = drm_get_format_info(dev, mode_cmd);

-

-	return drm_gem_fb_create(dev, file, mode_cmd);

-}

-

-static const struct drm_mode_config_funcs starfive_drm_mode_config_funcs = {

-	.fb_create = starfive_drm_mode_fb_create,

-	//.output_poll_changed = drm_fb_helper_output_poll_changed,

-	.atomic_check = drm_atomic_helper_check,

-	.atomic_commit = drm_atomic_helper_commit,

-};

-

-static const struct drm_mode_config_helper_funcs starfive_drm_mode_config_helpers = {

-	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,

-};

-

-static const struct file_operations starfive_drm_driver_fops = {

-	.owner = THIS_MODULE,

-	.open = drm_open,

-	.mmap = starfive_drm_gem_mmap,

-	.poll = drm_poll,

-	.read = drm_read,

-	.unlocked_ioctl = drm_ioctl,

-	.compat_ioctl = drm_compat_ioctl,

-	.release = drm_release,

-};

-

-static struct drm_driver starfive_drm_driver = {

-	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,

-	//.lastclose		= drm_fb_helper_lastclose,

-	.gem_vm_ops		= &drm_gem_cma_vm_ops,

-	.gem_free_object_unlocked = starfive_drm_gem_free_object,

-	.dumb_create		= starfive_drm_gem_dumb_create,

-	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,

-	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,

-	.gem_prime_get_sg_table	= starfive_drm_gem_prime_get_sg_table,

-	.gem_prime_import_sg_table	= starfive_drm_gem_prime_import_sg_table,

-	.gem_prime_vmap		= starfive_drm_gem_prime_vmap,

-	.gem_prime_vunmap	= starfive_drm_gem_prime_vunmap,

-	.gem_prime_mmap		= starfive_drm_gem_mmap_buf,

-	.fops			= &starfive_drm_driver_fops,

-	.name	= DRIVER_NAME,

-	.desc	= DRIVER_DESC,

-	.date	= DRIVER_DATE,

-	.major	= DRIVER_MAJOR,

-	.minor	= DRIVER_MINOR,

-};

-

-static int compare_dev(struct device *dev, void *data)

-{

-	return dev == (struct device *)data;

-}

-

-static void starfive_drm_match_add(struct device *dev,

-				  struct component_match **match,

-				  struct platform_driver *const *drivers,

-				  int count)

-{

-	int i;

-

-	for (i = 0; i < count; i++) {

-		struct device_driver *drv = &drivers[i]->driver;

-		struct device *p = NULL, *d;

-

-		while ((d = platform_find_device_by_driver(p, drv))) {

-			put_device(p);

-			component_match_add(dev, match, compare_dev, d);

-			p = d;

-		}

-		put_device(p);

-	}

-}

-

-static int starfive_drm_bind(struct device *dev)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	struct drm_device *drm_dev;

-	struct starfive_drm_private *private;

-	int ret;

-

-	drm_dev = drm_dev_alloc(&starfive_drm_driver, dev);

-	if (IS_ERR(drm_dev))

-		return PTR_ERR(drm_dev);

-

-	dev_set_drvdata(dev, drm_dev);

-

-	private = devm_kzalloc(drm_dev->dev, sizeof(*private), GFP_KERNEL);

-	if (!private) {

-		ret = -ENOMEM;

-		goto err_free;

-	}

-

-	drm_dev->dev_private = private;

-

-	/*ret = starfive_drm_init_iommu(drm_dev);

-	if (ret)

-		goto err_free;*/

-

-	ret = drmm_mode_config_init(drm_dev);

-	if (ret)

-		return ret;

-

-	drm_dev->mode_config.min_width = 64;

-	drm_dev->mode_config.min_height = 64;

-

-	/*

-	 * set max width and height as default value(4096x4096).

-	 * this value would be used to check framebuffer size limitation

-	 * at drm_mode_addfb().

-	 */

-	drm_dev->mode_config.max_width = 4096;

-	drm_dev->mode_config.max_height = 4096;

-	drm_dev->mode_config.funcs = &starfive_drm_mode_config_funcs;

-	drm_dev->mode_config.helper_private = &starfive_drm_mode_config_helpers;

-

-	ret = component_bind_all(dev, drm_dev);

-	if (ret)

-		goto err_component_bind_all;

-

-	ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc);

-	if (ret)

-		goto err_drm_vblank_init;

-

-	drm_mode_config_reset(drm_dev);

-

-	/*

-	 * enable drm irq mode.

-	 * - with irq_enabled = true, we can use the vblank feature.

-	 */

-	//drm_dev->irq_enabled = true;

-

-	/* init kms poll for handling hpd */

-	drm_kms_helper_poll_init(drm_dev);

-

-	ret = drm_dev_register(drm_dev, 0);

-	if (ret)

-		goto err_drm_dev_register;

-

-	drm_fbdev_generic_setup(drm_dev, 16);

-

-	return 0;

-

-err_drm_dev_register:

-	drm_kms_helper_poll_fini(drm_dev);

-err_drm_vblank_init:

-err_component_bind_all:

-err_free:

-	drm_dev_put(drm_dev);

-

-	return ret;

-}

-

-static void starfive_drm_unbind(struct device *dev)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	struct drm_device *drm_dev = dev_get_drvdata(dev);

-

-	drm_dev_unregister(drm_dev);

-	drm_kms_helper_poll_fini(drm_dev);

-	drm_atomic_helper_shutdown(drm_dev);

-	component_unbind_all(dev, drm_dev);

-	drm_mode_config_cleanup(drm_dev);

-

-	drm_dev_put(drm_dev);

-}

-

-static const struct component_master_ops starfive_drm_ops = {

-	.bind = starfive_drm_bind,

-	.unbind = starfive_drm_unbind,

-};

-

-static struct platform_driver * const starfive_component_drivers[] = {

-	&starfive_crtc_driver,

-	&starfive_dsi_platform_driver,

-	&starfive_encoder_driver,

-};

-

-static int starfive_drm_probe(struct platform_device *pdev)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	struct device *dev = &pdev->dev;

-	struct component_match *match = NULL;

-	int ret;

-

-	starfive_drm_match_add(dev, &match,

-					starfive_component_drivers, ARRAY_SIZE(starfive_component_drivers));

-	if (IS_ERR(match))

-		return PTR_ERR(match);

-

-	return component_master_add_with_match(dev, &starfive_drm_ops, match);

-}

-

-static int starfive_drm_remove(struct platform_device *pdev)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	component_master_del(&pdev->dev, &starfive_drm_ops);

-	return 0;

-}

-

-static const struct of_device_id starfive_drm_dt_ids[] = {

-	{ .compatible = "starfive,display-subsystem", },

-	{ /* sentinel */ },

-};

-MODULE_DEVICE_TABLE(of, starfive_drm_dt_ids);

-

-static struct platform_driver starfive_drm_platform_driver = {

-	.probe	= starfive_drm_probe,

-	.remove	= starfive_drm_remove,

-	.driver	= {

-		.name	= "starfive-drm",

-		.of_match_table = starfive_drm_dt_ids,

-		//.pm     = &starfive_drm_pm_ops,

-	},

-};

-

-static int __init starfive_drm_init(void)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	int ret;

-

-	ret = platform_register_drivers(starfive_component_drivers,

-					ARRAY_SIZE(starfive_component_drivers));

-	if (ret)

-		return ret;

-

-	return platform_driver_register(&starfive_drm_platform_driver);

-}

-

-static void __exit starfive_drm_exit(void)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	platform_driver_unregister(&starfive_drm_platform_driver);

-	platform_unregister_drivers(starfive_component_drivers,

-				    ARRAY_SIZE(starfive_component_drivers));

-}

-

-module_init(starfive_drm_init);

-module_exit(starfive_drm_exit);

-

-MODULE_AUTHOR("StarFive <StarFive@starfivetech.com>");

-MODULE_DESCRIPTION("StarFive SoC DRM driver");

-MODULE_LICENSE("GPL v2");

+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 StarFive Technology Co., Ltd
+ * Author: StarFive <StarFive@starfivetech.com>
+ */
+
+#include <linux/component.h>
+#include <linux/iommu.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/dma-mapping.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+#include "starfive_drm_drv.h"
+#include "starfive_drm_gem.h"
+
+#define DRIVER_NAME	"starfive"
+#define DRIVER_DESC	"starfive Soc DRM"
+#define DRIVER_DATE	"20210519"
+#define DRIVER_MAJOR	1
+#define DRIVER_MINOR	0
+
+static struct drm_framebuffer *
+starfive_drm_mode_fb_create(struct drm_device *dev, struct drm_file *file,
+		   const struct drm_mode_fb_cmd2 *mode_cmd)
+{
+	const struct drm_format_info *info = drm_get_format_info(dev, mode_cmd);
+
+	return drm_gem_fb_create(dev, file, mode_cmd);
+}
+
+static const struct drm_mode_config_funcs starfive_drm_mode_config_funcs = {
+	.fb_create = starfive_drm_mode_fb_create,
+	//.output_poll_changed = drm_fb_helper_output_poll_changed,
+	.atomic_check = drm_atomic_helper_check,
+	.atomic_commit = drm_atomic_helper_commit,
+};
+
+static const struct drm_mode_config_helper_funcs starfive_drm_mode_config_helpers = {
+	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
+};
+
+static const struct file_operations starfive_drm_driver_fops = {
+	.owner = THIS_MODULE,
+	.open = drm_open,
+	.mmap = starfive_drm_gem_mmap,
+	.poll = drm_poll,
+	.read = drm_read,
+	.unlocked_ioctl = drm_ioctl,
+	.compat_ioctl = drm_compat_ioctl,
+	.release = drm_release,
+};
+
+static struct drm_driver starfive_drm_driver = {
+	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
+	//.lastclose		= drm_fb_helper_lastclose,
+	.gem_vm_ops		= &drm_gem_cma_vm_ops,
+	.gem_free_object_unlocked = starfive_drm_gem_free_object,
+	.dumb_create		= starfive_drm_gem_dumb_create,
+	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
+	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
+	.gem_prime_get_sg_table	= starfive_drm_gem_prime_get_sg_table,
+	.gem_prime_import_sg_table	= starfive_drm_gem_prime_import_sg_table,
+	.gem_prime_vmap		= starfive_drm_gem_prime_vmap,
+	.gem_prime_vunmap	= starfive_drm_gem_prime_vunmap,
+	.gem_prime_mmap		= starfive_drm_gem_mmap_buf,
+	.fops			= &starfive_drm_driver_fops,
+	.name	= DRIVER_NAME,
+	.desc	= DRIVER_DESC,
+	.date	= DRIVER_DATE,
+	.major	= DRIVER_MAJOR,
+	.minor	= DRIVER_MINOR,
+};
+
+static int compare_dev(struct device *dev, void *data)
+{
+	return dev == (struct device *)data;
+}
+
+static void starfive_drm_match_add(struct device *dev,
+				  struct component_match **match,
+				  struct platform_driver *const *drivers,
+				  int count)
+{
+	int i;
+
+	for (i = 0; i < count; i++) {
+		struct device_driver *drv = &drivers[i]->driver;
+		struct device *p = NULL, *d;
+
+		while ((d = platform_find_device_by_driver(p, drv))) {
+			put_device(p);
+			component_match_add(dev, match, compare_dev, d);
+			p = d;
+		}
+		put_device(p);
+	}
+}
+
+static int starfive_drm_bind(struct device *dev)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	struct drm_device *drm_dev;
+	struct starfive_drm_private *private;
+	int ret;
+
+	drm_dev = drm_dev_alloc(&starfive_drm_driver, dev);
+	if (IS_ERR(drm_dev))
+		return PTR_ERR(drm_dev);
+
+	dev_set_drvdata(dev, drm_dev);
+
+	private = devm_kzalloc(drm_dev->dev, sizeof(*private), GFP_KERNEL);
+	if (!private) {
+		ret = -ENOMEM;
+		goto err_free;
+	}
+
+	drm_dev->dev_private = private;
+
+	//ret = starfive_drm_init_iommu(drm_dev);
+	//if (ret)
+	//	goto err_free;
+
+	ret = drmm_mode_config_init(drm_dev);
+	if (ret)
+		return ret;
+
+	drm_dev->mode_config.min_width = 64;
+	drm_dev->mode_config.min_height = 64;
+
+	/*
+	 * set max width and height as default value(4096x4096).
+	 * this value would be used to check framebuffer size limitation
+	 * at drm_mode_addfb().
+	 */
+	drm_dev->mode_config.max_width = 4096;
+	drm_dev->mode_config.max_height = 4096;
+	drm_dev->mode_config.funcs = &starfive_drm_mode_config_funcs;
+	drm_dev->mode_config.helper_private = &starfive_drm_mode_config_helpers;
+
+	ret = component_bind_all(dev, drm_dev);
+	if (ret)
+		goto err_component_bind_all;
+
+	ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc);
+	if (ret)
+		goto err_drm_vblank_init;
+
+	drm_mode_config_reset(drm_dev);
+
+	/*
+	 * enable drm irq mode.
+	 * - with irq_enabled = true, we can use the vblank feature.
+	 */
+	//drm_dev->irq_enabled = true;
+
+	/* init kms poll for handling hpd */
+	drm_kms_helper_poll_init(drm_dev);
+
+	ret = drm_dev_register(drm_dev, 0);
+	if (ret)
+		goto err_drm_dev_register;
+
+	drm_fbdev_generic_setup(drm_dev, 16);
+
+	return 0;
+
+err_drm_dev_register:
+	drm_kms_helper_poll_fini(drm_dev);
+err_drm_vblank_init:
+err_component_bind_all:
+err_free:
+	drm_dev_put(drm_dev);
+
+	return ret;
+}
+
+static void starfive_drm_unbind(struct device *dev)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	struct drm_device *drm_dev = dev_get_drvdata(dev);
+
+	drm_dev_unregister(drm_dev);
+	drm_kms_helper_poll_fini(drm_dev);
+	drm_atomic_helper_shutdown(drm_dev);
+	component_unbind_all(dev, drm_dev);
+	drm_mode_config_cleanup(drm_dev);
+
+	drm_dev_put(drm_dev);
+}
+
+static const struct component_master_ops starfive_drm_ops = {
+	.bind = starfive_drm_bind,
+	.unbind = starfive_drm_unbind,
+};
+
+static struct platform_driver * const starfive_component_drivers[] = {
+	&starfive_crtc_driver,
+	&starfive_dsi_platform_driver,
+	&starfive_encoder_driver,
+};
+
+static int starfive_drm_probe(struct platform_device *pdev)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	struct device *dev = &pdev->dev;
+	struct component_match *match = NULL;
+	int ret;
+
+	starfive_drm_match_add(dev, &match,
+					starfive_component_drivers, ARRAY_SIZE(starfive_component_drivers));
+	if (IS_ERR(match))
+		return PTR_ERR(match);
+
+	return component_master_add_with_match(dev, &starfive_drm_ops, match);
+}
+
+static int starfive_drm_remove(struct platform_device *pdev)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	component_master_del(&pdev->dev, &starfive_drm_ops);
+	return 0;
+}
+
+static const struct of_device_id starfive_drm_dt_ids[] = {
+	{ .compatible = "starfive,display-subsystem", },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, starfive_drm_dt_ids);
+
+static struct platform_driver starfive_drm_platform_driver = {
+	.probe	= starfive_drm_probe,
+	.remove	= starfive_drm_remove,
+	.driver	= {
+		.name	= "starfive-drm",
+		.of_match_table = starfive_drm_dt_ids,
+		//.pm     = &starfive_drm_pm_ops,
+	},
+};
+
+static int __init starfive_drm_init(void)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	int ret;
+
+	ret = platform_register_drivers(starfive_component_drivers,
+					ARRAY_SIZE(starfive_component_drivers));
+	if (ret)
+		return ret;
+
+	return platform_driver_register(&starfive_drm_platform_driver);
+}
+
+static void __exit starfive_drm_exit(void)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	platform_driver_unregister(&starfive_drm_platform_driver);
+	platform_unregister_drivers(starfive_component_drivers,
+				    ARRAY_SIZE(starfive_component_drivers));
+}
+
+module_init(starfive_drm_init);
+module_exit(starfive_drm_exit);
+
+MODULE_AUTHOR("StarFive <StarFive@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive SoC DRM driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/starfive/starfive_drm_drv.h b/drivers/gpu/drm/starfive/starfive_drm_drv.h
index c4dc20444710..9339ef8e4604 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_drv.h
+++ b/drivers/gpu/drm/starfive/starfive_drm_drv.h
@@ -1,33 +1,33 @@
-/* SPDX-License-Identifier: GPL-2.0-only */

-/*

- * Copyright (C) 2021 StarFive Technology Co., Ltd

- * Author: StarFive <StarFive@starfivetech.com>

- *

- */

-

-#ifndef _STARFIVE_DRM_DRV_H

-#define _STARFIVE_DRM_DRV_H

-

-#include <drm/drm_fb_helper.h>

-#include <drm/drm_atomic_helper.h>

-#include <drm/drm_gem.h>

-

-#include <linux/module.h>

-#include <linux/component.h>

-

-// #define USE_OLD_SCREEN  1

-

-struct starfive_drm_private {

-	struct drm_fb_helper fbdev_helper;

-	struct drm_gem_object *fbdev_bo;

-	struct mutex mm_lock;

-	struct drm_mm mm;

-};

-

-extern struct platform_driver starfive_crtc_driver;

-extern struct platform_driver starfive_encoder_driver;

-extern struct platform_driver starfive_dsi_platform_driver;

-extern int init_seeed_panel(void);

-extern void exit_seeed_panel(void);

-

-#endif /* _STARFIVE_DRM_DRV_H_ */

+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd
+ * Author: StarFive <StarFive@starfivetech.com>
+ *
+ */
+
+#ifndef _STARFIVE_DRM_DRV_H
+#define _STARFIVE_DRM_DRV_H
+
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_gem.h>
+
+#include <linux/module.h>
+#include <linux/component.h>
+
+// #define USE_OLD_SCREEN  1
+
+struct starfive_drm_private {
+	struct drm_fb_helper fbdev_helper;
+	struct drm_gem_object *fbdev_bo;
+	struct mutex mm_lock;
+	struct drm_mm mm;
+};
+
+extern struct platform_driver starfive_crtc_driver;
+extern struct platform_driver starfive_encoder_driver;
+extern struct platform_driver starfive_dsi_platform_driver;
+extern int init_seeed_panel(void);
+extern void exit_seeed_panel(void);
+
+#endif /* _STARFIVE_DRM_DRV_H_ */
diff --git a/drivers/gpu/drm/starfive/starfive_drm_dsi.c b/drivers/gpu/drm/starfive/starfive_drm_dsi.c
index 852c75761843..5f44aafc2fc3 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_dsi.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_dsi.c
@@ -29,8 +29,8 @@
 #include "starfive_drm_drv.h"
 
 //sysrst registers
-#define SRST_ASSERT0	    0x00
-#define SRST_STATUS0    	0x04
+#define SRST_ASSERT0		0x00
+#define SRST_STATUS0		0x04
 
 
 #define IP_CONF				0x0
@@ -473,16 +473,6 @@ struct cdns_dsi {
 	struct phy *dphy;
 };
 
-static void dump_mipi_reg(struct cdns_dsi *dsi)
-{
-	int i = 0;
-	uint32_t val = 0;
-	for (i = 0; i < 0x244; i+=4) {
-		val = readl(dsi->regs + i);
-		printk("dsi: addr = 0x%x, val = 0x%x\n", i, val);
-	}
-}
-
 static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
 {
 	return container_of(input, struct cdns_dsi, input);
@@ -595,17 +585,10 @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,
 	dsi_cfg->hfp = dpi_to_dsi_timing(mode_to_dpi_hfp(mode, mode_valid_check),
 					 bpp, DSI_HFP_FRAME_OVERHEAD);
 	//dpi to dsi transfer can not match , reconfig those parms
-	if(800 == mode->hdisplay)
-	{
-		#ifdef USE_OLD_SCREEN   //seeed panel
-		dsi_cfg->hsa = 16;
-		dsi_cfg->hbp = 199;
-		dsi_cfg->hfp = 153;
-		#else
+	if (800 == mode->hdisplay) {
 		dsi_cfg->hsa = 31;	//45-14
 		dsi_cfg->hbp = 103;	//115-12
 		dsi_cfg->hfp = 354; //360-6
-		#endif
 	}
 
 	return 0;
@@ -770,9 +753,6 @@ static void cdns_dsi_bridge_disable(struct drm_bridge *bridge)
 	struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
 	struct cdns_dsi *dsi = input_to_dsi(input);
 
-#if 0
-	dump_mipi_reg(dsi);
-#endif
 	u32 val;
 
 	dsi->link_initialized = false;
@@ -803,7 +783,7 @@ static void release_txbyte_rst(void)
 	do {
 		temp = readl(regs + SRST_STATUS0) >> 18;
 		temp &= 0x1;
-	} while (temp != 0x1 );
+	} while (temp != 0x1);
 	//udelay(1);
 }
 
@@ -827,7 +807,7 @@ static void cdns_dsi_hs_init(struct cdns_dsi *dsi)
 
 	phy_configure(dsi->dphy, &output->phy_opts);
 	phy_power_on(dsi->dphy);
-    release_txbyte_rst();
+	release_txbyte_rst();
 
 	writel(PLL_LOCKED, dsi->regs + MCTL_MAIN_STS_CLR);
 	writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN,
@@ -841,9 +821,8 @@ static void cdns_dsi_hs_init(struct cdns_dsi *dsi)
 	       dsi->regs + MCTL_DPHY_CFG0);
 
 	dpi_fifo_int = readl(dsi->regs + DPI_IRQ_CLR);
-    if (dpi_fifo_int) {
+	if (dpi_fifo_int)
 		writel(dsi->regs + DPI_IRQ_CLR, 1);
-    }
 }
 
 static void cdns_dsi_init_link(struct cdns_dsi *dsi)
@@ -892,7 +871,7 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)
 	struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;
 	unsigned long tx_byte_period;
 	struct cdns_dsi_cfg dsi_cfg;
-	u32 tmp, tmp2,reg_wakeup, div;
+	u32 tmp, tmp2, reg_wakeup, div;
 	int nlanes;
 
 	if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
@@ -944,44 +923,44 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)
 	writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp),
 	       dsi->regs + VID_DPHY_TIME);
 
-	writel(0xafffb,dsi->regs + MCTL_DPHY_TIMEOUT1);
+	writel(0xafffb, dsi->regs + MCTL_DPHY_TIMEOUT1);
 	writel(0x3ffff, dsi->regs + MCTL_DPHY_TIMEOUT2);
 	writel(0x3ab05, dsi->regs + MCTL_ULPOUT_TIME);
 
 	if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO) {
-	   switch (output->dev->format) {
-	   case MIPI_DSI_FMT_RGB888:
-		   tmp = VID_PIXEL_MODE_RGB888 |
-				 VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_24);
-		   break;
-
-	   case MIPI_DSI_FMT_RGB666:
-		   tmp = VID_PIXEL_MODE_RGB666 |
-				 VID_DATATYPE(MIPI_DSI_PIXEL_STREAM_3BYTE_18);
-		   break;
-
-	   case MIPI_DSI_FMT_RGB666_PACKED:
-		   tmp = VID_PIXEL_MODE_RGB666_PACKED |
-				 VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_18);
-		   break;
-
-	   case MIPI_DSI_FMT_RGB565:
-		   tmp = VID_PIXEL_MODE_RGB565 |
-				 VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_16);
-		   break;
-
-	   default:
-		   dev_err(dsi->base.dev, "Unsupported DSI format\n");
-		   return;
-	   }
-
-	   if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-		   tmp |= SYNC_PULSE_ACTIVE | SYNC_PULSE_HORIZONTAL;
+		switch (output->dev->format) {
+		case MIPI_DSI_FMT_RGB888:
+			tmp = VID_PIXEL_MODE_RGB888 |
+				VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_24);
+			break;
+
+		case MIPI_DSI_FMT_RGB666:
+			tmp = VID_PIXEL_MODE_RGB666 |
+				VID_DATATYPE(MIPI_DSI_PIXEL_STREAM_3BYTE_18);
+			break;
+
+		case MIPI_DSI_FMT_RGB666_PACKED:
+			tmp = VID_PIXEL_MODE_RGB666_PACKED |
+				VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_18);
+			break;
+
+		case MIPI_DSI_FMT_RGB565:
+			tmp = VID_PIXEL_MODE_RGB565 |
+				VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_16);
+			break;
+
+		default:
+			dev_err(dsi->base.dev, "Unsupported DSI format\n");
+			return;
+		}
+
+		if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+			tmp |= SYNC_PULSE_ACTIVE | SYNC_PULSE_HORIZONTAL;
 
 		tmp |= REG_BLKLINE_MODE(REG_BLK_MODE_BLANKING_PKT) |
-		       REG_BLKEOL_MODE(REG_BLK_MODE_BLANKING_PKT) |
-		       RECOVERY_MODE(RECOVERY_MODE_NEXT_HSYNC) |
-		       VID_IGNORE_MISS_VSYNC;
+			REG_BLKEOL_MODE(REG_BLK_MODE_BLANKING_PKT) |
+			RECOVERY_MODE(RECOVERY_MODE_NEXT_HSYNC) |
+			VID_IGNORE_MISS_VSYNC;
 
 		writel(tmp, dsi->regs + VID_MAIN_CTL);
 	}
@@ -1194,21 +1173,19 @@ static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,
 
 	do {
 		stat = readl(dsi->regs + DIRECT_CMD_STS);
-		if ((stat & 0x02) == 0x02) {
+		if ((stat & 0x02) == 0x02)
 			break;
-		}
 		mdelay(10);
 	} while (--timeout);
-	if (!timeout) {
+
+	if (!timeout)
 		DRM_DEBUG("timeout!\n");
-	}
 
 	stat_88 = readl(dsi->regs + DIRECT_CMD_STS);
 	stat_188 = readl(dsi->regs + MCTL_DPHY_ERR_FLAG);
 	stat_88_ack_val = stat_88 >> 16;
-	if (stat_188 || stat_88_ack_val) {
-		dev_dbg(host->dev,"stat: [188h] %08x, [88h] %08x\r\n", stat_188, stat_88);
-	}
+	if (stat_188 || stat_88_ack_val)
+		dev_dbg(host->dev, "stat: [188h] %08x, [88h] %08x\n", stat_188, stat_88);
 
 out:
 	pm_runtime_put(host->dev);
@@ -1258,7 +1235,8 @@ static int starfive_dsi_bind(struct device *dev, struct device *master, void *da
 	struct starfive_drm_private *private = drm_dev->dev_private;
 	int ret, irq;
 	u32 val;
-	dev_info(dev, "starfive_dsi_bind enter\n");
+
+	dev_info(dev, "%s enter\n", __func__);
 
 	dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
 	if (!dsi)
@@ -1274,9 +1252,7 @@ static int starfive_dsi_bind(struct device *dev, struct device *master, void *da
 
 	dsi->dphy = devm_phy_get(&pdev->dev, "dphy");
 	if (IS_ERR(dsi->dphy))
-	{
 		return PTR_ERR(dsi->dphy);
-	}
 
 	val = readl(dsi->regs + ID_REG);
 
diff --git a/drivers/gpu/drm/starfive/starfive_drm_encoder.c b/drivers/gpu/drm/starfive/starfive_drm_encoder.c
index f7fdbca31dbd..69313125d2e5 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_encoder.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_encoder.c
@@ -1,182 +1,179 @@
-// SPDX-License-Identifier: GPL-2.0-only

-/*

- * Copyright (c) 2021 StarFive Technology Co., Ltd

- * Author: StarFive <StarFive@starfivetech.com>

- */

-

-#include <linux/clk.h>

-#include <linux/component.h>

-#include <linux/of_device.h>

-

-#include <drm/drm_atomic.h>

-#include <drm/drm_atomic_helper.h>

-#include <drm/drm_atomic_uapi.h>

-#include <drm/drm_fb_cma_helper.h>

-#include <drm/drm_print.h>

-#include <drm/drm_probe_helper.h>

-#include <drm/drm_vblank.h>

-#include <drm/drm_of.h>

-

-#include "starfive_drm_drv.h"

-#include "starfive_drm_encoder.h"

-

-static struct starfive_encoder_data {

-	int endpoint_reg;

-	int encoder_type;

-};

-

-

-static void starfive_encoder_destroy(struct drm_encoder *encoder)

-{

-	drm_encoder_cleanup(encoder);

-}

-

-static const struct drm_encoder_funcs starfive_encoder_funcs = {

-	.destroy = starfive_encoder_destroy,

-};

-

-static int starfive_encoder_of_parse_ports(struct device *dev,

-				struct starfive_encoder_data **data)

-{

-	struct device_node *node = NULL;

-	struct device_node *remote = NULL;

-	struct starfive_encoder_data *encoder_data = NULL;

-	int ret, num_port = 0;

-

-	for_each_endpoint_of_node(dev->of_node, node) {

-

-		if (!of_device_is_available(node))

-			continue;

-

-		remote = of_graph_get_remote_port_parent(node);

-		if (!remote) {

-			dev_err(dev, "Cannot get remote parent\n");

-			ret = -EINVAL;

-			goto err_cleanup;

-		}

-

-		num_port++;

-	}

-

-	encoder_data = kzalloc(num_port * sizeof(*encoder_data), GFP_KERNEL);

-	*data = encoder_data;

-

-	for_each_endpoint_of_node(dev->of_node, node) {

-

-		if (!of_device_is_available(node))

-			continue;

-

-		of_property_read_u32(node, "encoder-type", &encoder_data->encoder_type);

-		of_property_read_u32(node, "reg", &encoder_data->endpoint_reg);

-		encoder_data ++;

-	}

-

-	return num_port;

-

-error_alloc:

-err_cleanup:

-	of_node_put(node);

-	return ret;

-}

-

-

-static int starfive_encoder_bind(struct device *dev, struct device *master, void *data)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	struct drm_device *drm_dev = data;

-	struct device_node *np = dev->of_node;

-	struct starfive_encoder *encoderp;

-	int ret;

-	int i = 0;

-

-	struct drm_panel *tmp_panel;

-	struct drm_bridge *tmp_bridge;

-	struct starfive_encoder_data *encoder_data = NULL;

-

-	u32 num_ports = 0;

-

-	num_ports = starfive_encoder_of_parse_ports(dev, &encoder_data);

-

-	encoderp = devm_kzalloc(dev, num_ports * sizeof(*encoderp), GFP_KERNEL);

-	if (!encoderp)

-		return -ENOMEM;

-

-	dev_set_drvdata(dev, encoderp);

-

-	for (i = 0; i < num_ports; i++) {

-		encoderp[i].dev = dev;

-		encoderp[i].drm_dev = drm_dev;

-		encoderp[i].data = &encoder_data[i];

-		encoderp[i].encoder.possible_crtcs = 0x1;

-

-		ret = drm_encoder_init(drm_dev, &encoderp[i].encoder, &starfive_encoder_funcs,

-				   encoder_data[i].encoder_type, NULL);

-		if (ret)

-			goto err_encoder;

-

-		ret = drm_of_find_panel_or_bridge(dev->of_node, 0,

-					encoder_data[i].endpoint_reg, &tmp_panel, &tmp_bridge);

-		if (ret) {

-			dev_err(dev,"endpoint returns %d\n", ret);

-		}

-

-		if (tmp_panel) {

-			DRM_DEBUG("found panel on endpoint \n");

-		}

-		if (tmp_bridge) {

-			DRM_DEBUG("found bridge on endpoint \n");

-		}

-

-		ret = drm_bridge_attach(&encoderp[i].encoder, tmp_bridge, NULL, 0);

-		if (ret)

-			goto err_bridge;

-	}

-

-	return 0;

-

-err_bridge:

-	drm_encoder_cleanup(&encoderp[i].encoder);

-err_encoder:

-	return ret;

-

-}

-

-static void starfive_encoder_unbind(struct device *dev, struct device *master, void *data)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	struct starfive_encoder *encoderp = dev_get_drvdata(dev);

-}

-

-static const struct component_ops starfive_encoder_component_ops = {

-	.bind   = starfive_encoder_bind,

-	.unbind = starfive_encoder_unbind,

-};

-

-static const struct of_device_id starfive_encoder_driver_dt_match[] = {

-	{ .compatible = "starfive,display-encoder",

-	  /*.data = &7100-crtc*/ },

-	{},

-};

-MODULE_DEVICE_TABLE(of, starfive_encoder_driver_dt_match);

-

-static int starfive_encoder_probe(struct platform_device *pdev)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	return component_add(&pdev->dev, &starfive_encoder_component_ops);

-}

-

-static int starfive_encoder_remove(struct platform_device *pdev)

-{

-	printk("-----%s: %d\n", __func__, __LINE__);

-	component_del(&pdev->dev, &starfive_encoder_component_ops);

-	return 0;

-}

-

-struct platform_driver starfive_encoder_driver = {

-	.probe = starfive_encoder_probe,

-	.remove = starfive_encoder_remove,

-	.driver = {

-		.name = "display-encoder",

-		.of_match_table = of_match_ptr(starfive_encoder_driver_dt_match),

-	},

-};

+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 StarFive Technology Co., Ltd
+ * Author: StarFive <StarFive@starfivetech.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic_uapi.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+#include <drm/drm_of.h>
+
+#include "starfive_drm_drv.h"
+#include "starfive_drm_encoder.h"
+
+static struct starfive_encoder_data {
+	int endpoint_reg;
+	int encoder_type;
+};
+
+
+static void starfive_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+}
+
+static const struct drm_encoder_funcs starfive_encoder_funcs = {
+	.destroy = starfive_encoder_destroy,
+};
+
+static int starfive_encoder_of_parse_ports(struct device *dev,
+				struct starfive_encoder_data **data)
+{
+	struct device_node *node = NULL;
+	struct device_node *remote = NULL;
+	struct starfive_encoder_data *encoder_data = NULL;
+	int ret, num_port = 0;
+
+	for_each_endpoint_of_node(dev->of_node, node) {
+
+		if (!of_device_is_available(node))
+			continue;
+
+		remote = of_graph_get_remote_port_parent(node);
+		if (!remote) {
+			dev_err(dev, "Cannot get remote parent\n");
+			ret = -EINVAL;
+			goto err_cleanup;
+		}
+
+		num_port++;
+	}
+
+	encoder_data = kzalloc(num_port * sizeof(*encoder_data), GFP_KERNEL);
+	*data = encoder_data;
+
+	for_each_endpoint_of_node(dev->of_node, node) {
+
+		if (!of_device_is_available(node))
+			continue;
+
+		of_property_read_u32(node, "encoder-type", &encoder_data->encoder_type);
+		of_property_read_u32(node, "reg", &encoder_data->endpoint_reg);
+		encoder_data++;
+	}
+
+	return num_port;
+
+error_alloc:
+err_cleanup:
+	of_node_put(node);
+	return ret;
+}
+
+
+static int starfive_encoder_bind(struct device *dev, struct device *master, void *data)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	struct drm_device *drm_dev = data;
+	struct device_node *np = dev->of_node;
+	struct starfive_encoder *encoderp;
+	int ret;
+	int i = 0;
+
+	struct drm_panel *tmp_panel;
+	struct drm_bridge *tmp_bridge;
+	struct starfive_encoder_data *encoder_data = NULL;
+
+	u32 num_ports = 0;
+
+	num_ports = starfive_encoder_of_parse_ports(dev, &encoder_data);
+
+	encoderp = devm_kzalloc(dev, num_ports * sizeof(*encoderp), GFP_KERNEL);
+	if (!encoderp)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, encoderp);
+
+	for (i = 0; i < num_ports; i++) {
+		encoderp[i].dev = dev;
+		encoderp[i].drm_dev = drm_dev;
+		encoderp[i].data = &encoder_data[i];
+		encoderp[i].encoder.possible_crtcs = 0x1;
+
+		ret = drm_encoder_init(drm_dev, &encoderp[i].encoder, &starfive_encoder_funcs,
+				   encoder_data[i].encoder_type, NULL);
+		if (ret)
+			goto err_encoder;
+
+		ret = drm_of_find_panel_or_bridge(dev->of_node, 0,
+					encoder_data[i].endpoint_reg, &tmp_panel, &tmp_bridge);
+		if (ret)
+			dev_err(dev, "endpoint returns %d\n", ret);
+
+		if (tmp_panel)
+			DRM_DEBUG("found panel on endpoint\n");
+
+		if (tmp_bridge)
+			DRM_DEBUG("found bridge on endpoint\n");
+
+		ret = drm_bridge_attach(&encoderp[i].encoder, tmp_bridge, NULL, 0);
+		if (ret)
+			goto err_bridge;
+	}
+
+	return 0;
+
+err_bridge:
+	drm_encoder_cleanup(&encoderp[i].encoder);
+err_encoder:
+	return ret;
+}
+
+static void starfive_encoder_unbind(struct device *dev, struct device *master, void *data)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	struct starfive_encoder *encoderp = dev_get_drvdata(dev);
+}
+
+static const struct component_ops starfive_encoder_component_ops = {
+	.bind   = starfive_encoder_bind,
+	.unbind = starfive_encoder_unbind,
+};
+
+static const struct of_device_id starfive_encoder_driver_dt_match[] = {
+	{ .compatible = "starfive,display-encoder",
+	  /*.data = &7100-crtc*/ },
+	{},
+};
+MODULE_DEVICE_TABLE(of, starfive_encoder_driver_dt_match);
+
+static int starfive_encoder_probe(struct platform_device *pdev)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	return component_add(&pdev->dev, &starfive_encoder_component_ops);
+}
+
+static int starfive_encoder_remove(struct platform_device *pdev)
+{
+	printk("-----%s: %d\n", __func__, __LINE__);
+	component_del(&pdev->dev, &starfive_encoder_component_ops);
+	return 0;
+}
+
+struct platform_driver starfive_encoder_driver = {
+	.probe = starfive_encoder_probe,
+	.remove = starfive_encoder_remove,
+	.driver = {
+		.name = "display-encoder",
+		.of_match_table = of_match_ptr(starfive_encoder_driver_dt_match),
+	},
+};
diff --git a/drivers/gpu/drm/starfive/starfive_drm_encoder.h b/drivers/gpu/drm/starfive/starfive_drm_encoder.h
index e3e5d746901a..c2a8a66e91f8 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_encoder.h
+++ b/drivers/gpu/drm/starfive/starfive_drm_encoder.h
@@ -1,20 +1,20 @@
-/* SPDX-License-Identifier: GPL-2.0-only */

-/*

- * Copyright (c) 2021 StarFive Technology Co., Ltd

- * Author: StarFive <StarFive@starfivetech.com>

- */

-

-#ifndef _STARFIVE_DRM_ENCODER_H

-#define _STARFIVE_DRM_ENCODER_H

-

-struct starfive_encoder {

-	struct drm_encoder		encoder;

-	struct device			*dev;

-	struct drm_device		*drm_dev;

-	bool is_enabled;

-	int encoder_type;

-	struct starfive_encoder_data *data;

-};

-#define to_starfive_encoder(x) container_of(x, struct starfive_encoder, encoder)

-

-#endif /* _STARFIVE_DRM_CRTC_H */

+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 StarFive Technology Co., Ltd
+ * Author: StarFive <StarFive@starfivetech.com>
+ */
+
+#ifndef _STARFIVE_DRM_ENCODER_H
+#define _STARFIVE_DRM_ENCODER_H
+
+struct starfive_encoder {
+	struct drm_encoder		encoder;
+	struct device			*dev;
+	struct drm_device		*drm_dev;
+	bool is_enabled;
+	int encoder_type;
+	struct starfive_encoder_data *data;
+};
+#define to_starfive_encoder(x) container_of(x, struct starfive_encoder, encoder)
+
+#endif /* _STARFIVE_DRM_CRTC_H */
diff --git a/drivers/gpu/drm/starfive/starfive_drm_gem.c b/drivers/gpu/drm/starfive/starfive_drm_gem.c
index 7755a2ba2271..4eb59f275faa 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_gem.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_gem.c
@@ -1,329 +1,332 @@
-// SPDX-License-Identifier: GPL-2.0-only

-/*

- * Copyright (c) 2021 StarFive Technology Co., Ltd

- * Author: StarFive <StarFive@starfivetech.com>

- */

-

-#include <linux/dma-buf.h>

-#include <linux/iommu.h>

-#include <linux/vmalloc.h>

-

-#include <drm/drm.h>

-#include <drm/drm_gem.h>

-#include <drm/drm_prime.h>

-#include <drm/drm_vma_manager.h>

-

-#include "starfive_drm_drv.h"

-#include "starfive_drm_gem.h"

-

-static int starfive_drm_gem_object_mmap_dma(struct drm_gem_object *obj,

-					    struct vm_area_struct *vma)

-{

-	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);

-	struct drm_device *drm = obj->dev;

-

-	return dma_mmap_attrs(drm->dev, vma, starfive_obj->kvaddr,

-			starfive_obj->dma_addr, obj->size, starfive_obj->dma_attrs);

-}

-

-static int starfive_drm_gem_object_mmap(struct drm_gem_object *obj,

-					struct vm_area_struct *vma)

-{

-	int ret;

-	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);

-

-	/*

-	 * We allocated a struct page table for rk_obj, so clear

-	 * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap().

-	 */

-	vma->vm_flags &= ~VM_PFNMAP;

-

-	ret = starfive_drm_gem_object_mmap_dma(obj, vma);

-

-	if (ret)

-		drm_gem_vm_close(vma);

-

-	return ret;

-}

-

-int starfive_drm_gem_mmap_buf(struct drm_gem_object *obj,

-				struct vm_area_struct *vma)

-{

-	int ret;

-	ret = drm_gem_mmap_obj(obj, obj->size, vma);

-	if (ret)

-		return ret;

-

-	return starfive_drm_gem_object_mmap(obj, vma);

-

-}

-

-int starfive_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)

-{

-	struct drm_gem_object *obj;

-	int ret;

-

-	ret = drm_gem_mmap(filp, vma);

-	if (ret)

-		return ret;

-

-	obj = vma->vm_private_data;

-

-	/*

-	* Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the

-	* whole buffer from the start.

-	*/

-	vma->vm_pgoff = 0;

-

-	return starfive_drm_gem_object_mmap(obj, vma);

-}

-

-

-void starfive_drm_gem_free_object(struct drm_gem_object *obj)

-{

-	struct starfive_drm_gem_obj *starfive_gem = to_starfive_gem_obj(obj);

-	struct drm_device *drm_dev = obj->dev;

-

-	if (starfive_gem->sg)

-		drm_prime_gem_destroy(obj, starfive_gem->sg);

-	else

-		dma_free_attrs(drm_dev->dev, obj->size, starfive_gem->kvaddr,

-				starfive_gem->dma_addr, starfive_gem->dma_attrs);

-

-	/* release file pointer to gem object. */

-	drm_gem_object_release(obj);

-

-	kfree(starfive_gem);

-}

-

-static struct starfive_drm_gem_obj *

-	starfive_drm_gem_alloc_object(struct drm_device *drm, unsigned int size)

-{

-	struct starfive_drm_gem_obj *starfive_obj;

-	struct drm_gem_object *obj;

-

-	size = round_up(size, PAGE_SIZE);

-	starfive_obj = kzalloc(sizeof(*starfive_obj), GFP_KERNEL);

-	if (!starfive_obj)

-		return ERR_PTR(-ENOMEM);

-

-	obj = &starfive_obj->base;

-	drm_gem_object_init(drm, obj, size);

-

-	return starfive_obj;

-}

-

-static int starfive_drm_gem_alloc_dma(struct starfive_drm_gem_obj *starfive_obj,

-				bool alloc_kmap)

-{

-	struct drm_gem_object *obj = &starfive_obj->base;

-	struct drm_device *drm = obj->dev;

-	struct starfive_drm_private *private = drm->dev_private;

-	starfive_obj->dma_attrs = DMA_ATTR_WRITE_COMBINE;

-

-	if (!alloc_kmap)

-		starfive_obj->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;

-

-	starfive_obj->kvaddr = dma_alloc_attrs(drm->dev, obj->size,

-							&starfive_obj->dma_addr, GFP_KERNEL,

-							starfive_obj->dma_attrs);

-

-	DRM_INFO("kvaddr = 0x%px\n", starfive_obj->kvaddr);

-	DRM_INFO("dma_addr = 0x%x, size = %d \n", starfive_obj->dma_addr, obj->size);

-	if (!starfive_obj->kvaddr) {

-		DRM_ERROR("failed to allocate %zu byte dma buffer", obj->size);

-		return -ENOMEM;

-	}

-

-	return 0;

-}

-

-static int starfive_drm_gem_alloc_buf(struct starfive_drm_gem_obj *starfive_obj,

-				bool alloc_kmap)

-{

-	return starfive_drm_gem_alloc_dma(starfive_obj, alloc_kmap);

-}

-

-static void starfive_drm_gem_release_object(struct starfive_drm_gem_obj *starfive_obj)

-{

-	drm_gem_object_release(&starfive_obj->base);

-	kfree(starfive_obj);

-}

-

-struct starfive_drm_gem_obj *

-starfive_drm_gem_create_object(struct drm_device *drm, unsigned int size,

-				bool alloc_kmap)

-{

-	struct starfive_drm_gem_obj *starfive_obj;

-	int ret;

-

-	starfive_obj = starfive_drm_gem_alloc_object(drm, size);

-	if (IS_ERR(starfive_obj))

-		return starfive_obj;

-

-	ret = starfive_drm_gem_alloc_buf(starfive_obj, alloc_kmap);

-	if (ret)

-		goto err_free_obj;

-

-	return starfive_obj;

-

-err_free_obj:

-	starfive_drm_gem_release_object(starfive_obj);

-	return ERR_PTR(ret);

-}

-

-static struct starfive_drm_gem_obj *

-starfive_drm_gem_create_with_handle(struct drm_file *file_priv,

-				struct drm_device *drm, unsigned int size,

-				unsigned int *handle)

-{

-	struct starfive_drm_gem_obj *starfive_gem;

-	struct drm_gem_object *gem;

-	int ret;

-

-#ifdef CONFIG_FRAMEBUFFER_CONSOLE

-	starfive_gem = starfive_drm_gem_create_object(drm, size, true);//config true,for console display

-#else	

-	starfive_gem = starfive_drm_gem_create_object(drm, size, false);

-#endif

-	if (IS_ERR(starfive_gem))

-		return ERR_CAST(starfive_gem);

-

-	gem = &starfive_gem->base;

-

-	/*

-	 * allocate a id of idr table where the obj is registered

-	 * and handle has the id what user can see.

-	 */

-	ret = drm_gem_handle_create(file_priv, gem, handle);

-	if (ret)

-		goto err_handle_create;

-

-	/* drop reference from allocate - handle holds it now. */

-	drm_gem_object_put(gem);

-

-	return starfive_gem;

-

-err_handle_create:

-	starfive_drm_gem_free_object(gem);

-

-	return ERR_PTR(ret);

-}

-

-int starfive_drm_gem_dumb_create(struct drm_file *file_priv,

-			     struct drm_device *dev,

-			     struct drm_mode_create_dumb *args)

-{

-	struct starfive_drm_gem_obj *starfive_gem;

-

-	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);

-	args->size = args->pitch * args->height;

-	/*

-	 * align to 64 bytes since Mali requires it.

-	 */

-	//args->pitch = ALIGN(min_pitch, 64);

-

-	starfive_gem = starfive_drm_gem_create_with_handle(file_priv, dev,

-					args->size, &args->handle);

-

-	return PTR_ERR_OR_ZERO(starfive_gem);

-}

-

-struct sg_table *starfive_drm_gem_prime_get_sg_table(struct drm_gem_object *obj)

-{

-	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);

-	struct drm_device *drm = obj->dev;

-	struct sg_table *sgt;

-	int ret;

-

-	if (starfive_obj->pages)

-		return drm_prime_pages_to_sg(obj->dev, starfive_obj->pages, starfive_obj->num_pages);

-

-	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);

-	if (!sgt)

-		return ERR_PTR(-ENOMEM);

-

-	ret = dma_get_sgtable_attrs(drm->dev, sgt, starfive_obj->kvaddr, starfive_obj->dma_addr,

-			obj->size, starfive_obj->dma_attrs);

-	if (ret) {

-		DRM_ERROR("failed to allocate sgt, %d\n", ret);

-		kfree(sgt);

-		return ERR_PTR(ret);

-	}

-

-	return sgt;

-}

-

-static int

-starfive_drm_gem_dma_map_sg(struct drm_device *drm,

-			struct dma_buf_attachment *attach,

-			struct sg_table *sg,

-			struct starfive_drm_gem_obj *starfive_obj)

-{

-	int err = dma_map_sgtable(drm->dev, sg, DMA_BIDIRECTIONAL, 0);

-	if (err)

-		return err;

-

-	if (drm_prime_get_contiguous_size(sg) < attach->dmabuf->size) {

-		DRM_ERROR("failed to map sg_table to contiguous linear address.\n");

-		dma_unmap_sgtable(drm->dev, sg, DMA_BIDIRECTIONAL, 0);

-		return -EINVAL;

-	}

-

-	starfive_obj->dma_addr = sg_dma_address(sg->sgl);

-	starfive_obj->sg = sg;

-	return 0;

-}

-

-struct drm_gem_object *

-starfive_drm_gem_prime_import_sg_table(struct drm_device *drm,

-				struct dma_buf_attachment *attach,

-				struct sg_table *sg)

-{

-	struct starfive_drm_private *private = drm->dev_private;

-	struct starfive_drm_gem_obj *starfive_obj;

-	int ret;

-

-	starfive_obj = starfive_drm_gem_alloc_object(drm, attach->dmabuf->size);

-	if (IS_ERR(starfive_obj))

-		return ERR_CAST(starfive_obj);

-

-	ret = starfive_drm_gem_dma_map_sg(drm, attach, sg, starfive_obj);

-

-	if (ret < 0) {

-		DRM_ERROR("failed to import sg table: %d\n", ret);

-		goto err_free_obj;

-	}

-

-	return &starfive_obj->base;

-

-err_free_obj:

-	starfive_drm_gem_release_object(starfive_obj);

-	return ERR_PTR(ret);

-}

-

-void *starfive_drm_gem_prime_vmap(struct drm_gem_object *obj)

-{

-	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);

-

-	if (starfive_obj->pages)

-		return vmap(starfive_obj->pages, starfive_obj->num_pages, VM_MAP,

-			    pgprot_writecombine(PAGE_KERNEL));

-

-	if (starfive_obj->dma_attrs & DMA_ATTR_NO_KERNEL_MAPPING)

-	{

-		return NULL;

-	}

-	return starfive_obj->kvaddr;

-}

-

-void starfive_drm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)

-{

-	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);

-

-	if (starfive_obj->pages) {

-		vunmap(vaddr);

-		return;

-	}

-	/* Nothing to do if allocated by DMA mapping API. */

-}

+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 StarFive Technology Co., Ltd
+ * Author: StarFive <StarFive@starfivetech.com>
+ */
+
+#include <linux/dma-buf.h>
+#include <linux/iommu.h>
+#include <linux/vmalloc.h>
+
+#include <drm/drm.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_prime.h>
+#include <drm/drm_vma_manager.h>
+
+#include "starfive_drm_drv.h"
+#include "starfive_drm_gem.h"
+
+static int starfive_drm_gem_object_mmap_dma(struct drm_gem_object *obj,
+					    struct vm_area_struct *vma)
+{
+	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
+	struct drm_device *drm = obj->dev;
+
+	return dma_mmap_attrs(drm->dev, vma, starfive_obj->kvaddr,
+			starfive_obj->dma_addr, obj->size, starfive_obj->dma_attrs);
+}
+
+static int starfive_drm_gem_object_mmap(struct drm_gem_object *obj,
+					struct vm_area_struct *vma)
+{
+	int ret;
+	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
+
+	/*
+	 * We allocated a struct page table for rk_obj, so clear
+	 * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap().
+	 */
+	vma->vm_flags &= ~VM_PFNMAP;
+
+	ret = starfive_drm_gem_object_mmap_dma(obj, vma);
+
+	if (ret)
+		drm_gem_vm_close(vma);
+
+	return ret;
+}
+
+int starfive_drm_gem_mmap_buf(struct drm_gem_object *obj,
+				struct vm_area_struct *vma)
+{
+	int ret;
+
+	ret = drm_gem_mmap_obj(obj, obj->size, vma);
+	if (ret)
+		return ret;
+
+	return starfive_drm_gem_object_mmap(obj, vma);
+
+}
+
+int starfive_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	struct drm_gem_object *obj;
+	int ret;
+
+	ret = drm_gem_mmap(filp, vma);
+	if (ret)
+		return ret;
+
+	obj = vma->vm_private_data;
+
+	/*
+	 * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the
+	 * whole buffer from the start.
+	 */
+	vma->vm_pgoff = 0;
+
+	return starfive_drm_gem_object_mmap(obj, vma);
+}
+
+
+void starfive_drm_gem_free_object(struct drm_gem_object *obj)
+{
+	struct starfive_drm_gem_obj *starfive_gem = to_starfive_gem_obj(obj);
+	struct drm_device *drm_dev = obj->dev;
+
+	if (starfive_gem->sg)
+		drm_prime_gem_destroy(obj, starfive_gem->sg);
+	else
+		dma_free_attrs(drm_dev->dev, obj->size, starfive_gem->kvaddr,
+				starfive_gem->dma_addr, starfive_gem->dma_attrs);
+
+	/* release file pointer to gem object. */
+	drm_gem_object_release(obj);
+
+	kfree(starfive_gem);
+}
+
+static struct starfive_drm_gem_obj *
+	starfive_drm_gem_alloc_object(struct drm_device *drm, unsigned int size)
+{
+	struct starfive_drm_gem_obj *starfive_obj;
+	struct drm_gem_object *obj;
+
+	size = round_up(size, PAGE_SIZE);
+	starfive_obj = kzalloc(sizeof(*starfive_obj), GFP_KERNEL);
+	if (!starfive_obj)
+		return ERR_PTR(-ENOMEM);
+
+	obj = &starfive_obj->base;
+	drm_gem_object_init(drm, obj, size);
+
+	return starfive_obj;
+}
+
+static int starfive_drm_gem_alloc_dma(struct starfive_drm_gem_obj *starfive_obj,
+				bool alloc_kmap)
+{
+	struct drm_gem_object *obj = &starfive_obj->base;
+	struct drm_device *drm = obj->dev;
+	struct starfive_drm_private *private = drm->dev_private;
+
+	starfive_obj->dma_attrs = DMA_ATTR_WRITE_COMBINE;
+
+	if (!alloc_kmap)
+		starfive_obj->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
+
+	starfive_obj->kvaddr = dma_alloc_attrs(drm->dev, obj->size,
+							&starfive_obj->dma_addr, GFP_KERNEL,
+							starfive_obj->dma_attrs);
+
+	DRM_INFO("kvaddr = 0x%x\n", starfive_obj->kvaddr);
+	DRM_INFO("dma_addr = 0x%x, size = %d\n", starfive_obj->dma_addr, obj->size);
+	if (!starfive_obj->kvaddr) {
+		DRM_ERROR("failed to allocate %zu byte dma buffer", obj->size);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int starfive_drm_gem_alloc_buf(struct starfive_drm_gem_obj *starfive_obj,
+				bool alloc_kmap)
+{
+	return starfive_drm_gem_alloc_dma(starfive_obj, alloc_kmap);
+}
+
+static void starfive_drm_gem_release_object(struct starfive_drm_gem_obj *starfive_obj)
+{
+	drm_gem_object_release(&starfive_obj->base);
+	kfree(starfive_obj);
+}
+
+struct starfive_drm_gem_obj *
+starfive_drm_gem_create_object(struct drm_device *drm, unsigned int size,
+				bool alloc_kmap)
+{
+	struct starfive_drm_gem_obj *starfive_obj;
+	int ret;
+
+	starfive_obj = starfive_drm_gem_alloc_object(drm, size);
+	if (IS_ERR(starfive_obj))
+		return starfive_obj;
+
+	ret = starfive_drm_gem_alloc_buf(starfive_obj, alloc_kmap);
+	if (ret)
+		goto err_free_obj;
+
+	return starfive_obj;
+
+err_free_obj:
+	starfive_drm_gem_release_object(starfive_obj);
+	return ERR_PTR(ret);
+}
+
+static struct starfive_drm_gem_obj *
+starfive_drm_gem_create_with_handle(struct drm_file *file_priv,
+				struct drm_device *drm, unsigned int size,
+				unsigned int *handle)
+{
+	struct starfive_drm_gem_obj *starfive_gem;
+	struct drm_gem_object *gem;
+	int ret;
+
+#ifdef CONFIG_FRAMEBUFFER_CONSOLE
+	starfive_gem = starfive_drm_gem_create_object(drm, size, true);//config true,for console display
+#else
+	starfive_gem = starfive_drm_gem_create_object(drm, size, false);
+#endif
+	if (IS_ERR(starfive_gem))
+		return ERR_CAST(starfive_gem);
+
+	gem = &starfive_gem->base;
+
+	/*
+	 * allocate a id of idr table where the obj is registered
+	 * and handle has the id what user can see.
+	 */
+	ret = drm_gem_handle_create(file_priv, gem, handle);
+	if (ret)
+		goto err_handle_create;
+
+	/* drop reference from allocate - handle holds it now. */
+	drm_gem_object_put(gem);
+
+	return starfive_gem;
+
+err_handle_create:
+	starfive_drm_gem_free_object(gem);
+
+	return ERR_PTR(ret);
+}
+
+int starfive_drm_gem_dumb_create(struct drm_file *file_priv,
+			     struct drm_device *dev,
+			     struct drm_mode_create_dumb *args)
+{
+	struct starfive_drm_gem_obj *starfive_gem;
+
+	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+	args->size = args->pitch * args->height;
+	/*
+	 * align to 64 bytes since Mali requires it.
+	 */
+	//args->pitch = ALIGN(min_pitch, 64);
+
+	starfive_gem = starfive_drm_gem_create_with_handle(file_priv, dev,
+					args->size, &args->handle);
+
+	return PTR_ERR_OR_ZERO(starfive_gem);
+}
+
+struct sg_table *starfive_drm_gem_prime_get_sg_table(struct drm_gem_object *obj)
+{
+	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
+	struct drm_device *drm = obj->dev;
+	struct sg_table *sgt;
+	int ret;
+
+	if (starfive_obj->pages)
+		return drm_prime_pages_to_sg(obj->dev, starfive_obj->pages, starfive_obj->num_pages);
+
+	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt)
+		return ERR_PTR(-ENOMEM);
+
+	ret = dma_get_sgtable_attrs(drm->dev, sgt, starfive_obj->kvaddr, starfive_obj->dma_addr,
+			obj->size, starfive_obj->dma_attrs);
+	if (ret) {
+		DRM_ERROR("failed to allocate sgt, %d\n", ret);
+		kfree(sgt);
+		return ERR_PTR(ret);
+	}
+
+	return sgt;
+}
+
+static int
+starfive_drm_gem_dma_map_sg(struct drm_device *drm,
+			struct dma_buf_attachment *attach,
+			struct sg_table *sg,
+			struct starfive_drm_gem_obj *starfive_obj)
+{
+	int err;
+
+	err = dma_map_sgtable(drm->dev, sg, DMA_BIDIRECTIONAL, 0);
+	if (err)
+		return err;
+
+	if (drm_prime_get_contiguous_size(sg) < attach->dmabuf->size) {
+		DRM_ERROR("failed to map sg_table to contiguous linear address.\n");
+		dma_unmap_sgtable(drm->dev, sg, DMA_BIDIRECTIONAL, 0);
+		return -EINVAL;
+	}
+
+	starfive_obj->dma_addr = sg_dma_address(sg->sgl);
+	starfive_obj->sg = sg;
+	return 0;
+}
+
+struct drm_gem_object *
+starfive_drm_gem_prime_import_sg_table(struct drm_device *drm,
+				struct dma_buf_attachment *attach,
+				struct sg_table *sg)
+{
+	struct starfive_drm_private *private = drm->dev_private;
+	struct starfive_drm_gem_obj *starfive_obj;
+	int ret;
+
+	starfive_obj = starfive_drm_gem_alloc_object(drm, attach->dmabuf->size);
+	if (IS_ERR(starfive_obj))
+		return ERR_CAST(starfive_obj);
+
+	ret = starfive_drm_gem_dma_map_sg(drm, attach, sg, starfive_obj);
+
+	if (ret < 0) {
+		DRM_ERROR("failed to import sg table: %d\n", ret);
+		goto err_free_obj;
+	}
+
+	return &starfive_obj->base;
+
+err_free_obj:
+	starfive_drm_gem_release_object(starfive_obj);
+	return ERR_PTR(ret);
+}
+
+void *starfive_drm_gem_prime_vmap(struct drm_gem_object *obj)
+{
+	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
+
+	if (starfive_obj->pages)
+		return vmap(starfive_obj->pages, starfive_obj->num_pages, VM_MAP,
+			    pgprot_writecombine(PAGE_KERNEL));
+
+	if (starfive_obj->dma_attrs & DMA_ATTR_NO_KERNEL_MAPPING)
+		return NULL;
+
+	return starfive_obj->kvaddr;
+}
+
+void starfive_drm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
+{
+	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
+
+	if (starfive_obj->pages) {
+		vunmap(vaddr);
+		return;
+	}
+	/* Nothing to do if allocated by DMA mapping API. */
+}
diff --git a/drivers/gpu/drm/starfive/starfive_drm_gem.h b/drivers/gpu/drm/starfive/starfive_drm_gem.h
index d1a5cb857ed7..5d4bb8e3d4da 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_gem.h
+++ b/drivers/gpu/drm/starfive/starfive_drm_gem.h
@@ -1,41 +1,41 @@
-/* SPDX-License-Identifier: GPL-2.0-only */

-/*

- * Copyright (c) 2021 StarFive Technology Co., Ltd

- * Author: StarFive <StarFive@starfivetech.com>

- */

-

-#ifndef _STARFIVE_DRM_GEM_H

-#define _STARFIVE_DRM_GEM_H

-

-#include <drm/drm_gem.h>

-

-struct starfive_drm_gem_obj {

-	struct drm_gem_object	base;

-	//void			*cookie; //mtk

-	void			*kvaddr;

-	dma_addr_t		dma_addr;

-	unsigned long		dma_attrs;

-

-	/* Used when IOMMU is enabled */

-	unsigned long	num_pages;

-	struct sg_table		*sg;

-	struct page		**pages;

-};

-#define to_starfive_gem_obj(x)	container_of(x, struct starfive_drm_gem_obj, base)

-

-

-void starfive_drm_gem_free_object(struct drm_gem_object *obj);

-int starfive_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);

-int starfive_drm_gem_mmap_buf(struct drm_gem_object *obj,

-			  struct vm_area_struct *vma);

-int starfive_drm_gem_dumb_create(struct drm_file *file_priv,

-			     struct drm_device *dev,

-			     struct drm_mode_create_dumb *args);

-struct sg_table *starfive_drm_gem_prime_get_sg_table(struct drm_gem_object *obj);

-struct drm_gem_object *

-starfive_drm_gem_prime_import_sg_table(struct drm_device *dev,

-				   struct dma_buf_attachment *attach,

-				   struct sg_table *sg);

-void *starfive_drm_gem_prime_vmap(struct drm_gem_object *obj);

-void starfive_drm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);

-#endif /* _STARFIVE_DRM_GEM_H */

+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 StarFive Technology Co., Ltd
+ * Author: StarFive <StarFive@starfivetech.com>
+ */
+
+#ifndef _STARFIVE_DRM_GEM_H
+#define _STARFIVE_DRM_GEM_H
+
+#include <drm/drm_gem.h>
+
+struct starfive_drm_gem_obj {
+	struct drm_gem_object	base;
+	//void			*cookie; //mtk
+	void			*kvaddr;
+	dma_addr_t		dma_addr;
+	unsigned long		dma_attrs;
+
+	/* Used when IOMMU is enabled */
+	unsigned long	num_pages;
+	struct sg_table		*sg;
+	struct page		**pages;
+};
+#define to_starfive_gem_obj(x)	container_of(x, struct starfive_drm_gem_obj, base)
+
+
+void starfive_drm_gem_free_object(struct drm_gem_object *obj);
+int starfive_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
+int starfive_drm_gem_mmap_buf(struct drm_gem_object *obj,
+			  struct vm_area_struct *vma);
+int starfive_drm_gem_dumb_create(struct drm_file *file_priv,
+			     struct drm_device *dev,
+			     struct drm_mode_create_dumb *args);
+struct sg_table *starfive_drm_gem_prime_get_sg_table(struct drm_gem_object *obj);
+struct drm_gem_object *
+starfive_drm_gem_prime_import_sg_table(struct drm_device *dev,
+				   struct dma_buf_attachment *attach,
+				   struct sg_table *sg);
+void *starfive_drm_gem_prime_vmap(struct drm_gem_object *obj);
+void starfive_drm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
+#endif /* _STARFIVE_DRM_GEM_H */
diff --git a/drivers/gpu/drm/starfive/starfive_drm_lcdc.c b/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
index 233d0746c439..4aef1c4968e3 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
@@ -1,18 +1,18 @@
 /* driver/video/starfive/starfive_lcdc.c
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License version 2 as
-** published by the Free Software Foundation.
-**
-** Copyright (C) 2020 StarFive, Inc.
-**
-** PURPOSE:	This files contains the driver of LCD controller.
-**
-** CHANGE HISTORY:
-**	Version		Date		Author		Description
-**	0.1.0		2020-11-03	starfive		created
-**
-*/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (C) 2020 StarFive, Inc.
+ *
+ * PURPOSE:	This files contains the driver of LCD controller.
+ *
+ * CHANGE HISTORY:
+ *	Version		Date		Author		Description
+ *	0.1.0		2020-11-03	starfive		created
+ *
+ */
 
 #include <linux/module.h>
 #include <video/starfive_fb.h>
@@ -24,13 +24,13 @@
 
 //#define SF_LCDC_DEBUG	1
 #ifdef SF_LCDC_DEBUG
-	#define LCDC_PRT(format, args...)  printk(KERN_DEBUG "[LCDC]: " format, ## args)
-	#define LCDC_INFO(format, args...) printk(KERN_INFO "[LCDC]: " format, ## args)
+	#define LCDC_PRT(format, args...)	printk(KERN_DEBUG "[LCDC]: " format, ## args)
+	#define LCDC_INFO(format, args...)	printk(KERN_INFO "[LCDC]: " format, ## args)
 	#define LCDC_ERR(format, args...)	printk(KERN_ERR "[LCDC]: " format, ## args)
 #else
-	#define LCDC_PRT(x...)  do{} while(0)
-	#define LCDC_INFO(x...)  do{} while(0)
-	#define LCDC_ERR(x...)  do{} while(0)
+	#define LCDC_PRT(x...)	do {} while (0)
+	#define LCDC_INFO(x...)	do {} while (0)
+	#define LCDC_ERR(x...)	do {} while (0)
 #endif
 
 static const struct res_name mem_res_name[] = {
@@ -76,8 +76,8 @@ static void starfive_lcdc_rstwrite32(struct starfive_crtc *sf_crtc, u32 reg, u32
 void lcdc_mode_cfg(struct starfive_crtc *sf_crtc, uint32_t workMode, int dotEdge, int syncEdge, int r2yBypass,
 					int srcSel, int intSrc, int intFreq)
 {
-  u32 lcdcEn = 0x1;
-  u32 cfg = lcdcEn | workMode << LCDC_WORK_MODE
+	u32 lcdcEn = 0x1;
+	u32 cfg = lcdcEn | workMode << LCDC_WORK_MODE
 				| dotEdge << LCDC_DOTCLK_P
 				| syncEdge << LCDC_HSYNC_P
 				| syncEdge << LCDC_VSYNC_P
@@ -87,8 +87,8 @@ void lcdc_mode_cfg(struct starfive_crtc *sf_crtc, uint32_t workMode, int dotEdge
 				| intSrc << LCDC_INT_SEL
 				| intFreq << LCDC_INT_FREQ;
 
-  sf_fb_lcdcwrite32(sf_crtc, LCDC_GCTRL, cfg);
-  LCDC_PRT("LCDC WorkMode: 0x%x, LCDC Path: %d\n", workMode, srcSel);
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_GCTRL, cfg);
+	LCDC_PRT("LCDC WorkMode: 0x%x, LCDC Path: %d\n", workMode, srcSel);
 }
 
 void lcdc_timing_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state, int vunit)
@@ -115,7 +115,7 @@ void lcdc_timing_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state
 	vbk = vsync_len + upper_margin;
 	vfp = lower_margin;
 
- 	LCDC_PRT(" %s : h-sync = %d, h-bp = %d, h-fp = %d", __func__, hsync_len, left_margin, right_margin);
+	LCDC_PRT(" %s : h-sync = %d, h-bp = %d, h-fp = %d", __func__, hsync_len, left_margin, right_margin);
 	LCDC_PRT(" %s : v-sync = %d, v-bp = %d, v-fp = %d", __func__, vsync_len, upper_margin, lower_margin);
 
 	int htiming = hbk | hfp << LCDC_RGB_HFP;
@@ -134,21 +134,20 @@ void lcdc_timing_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state
 //lcdc_desize_cfg(sf_dev, sf_dev->display_info.xres-1, sf_dev->display_info.yres-1);
 void lcdc_desize_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
 {
-  int hsize = state->adjusted_mode.crtc_hdisplay - 1;
-  int vsize = state->adjusted_mode.crtc_vdisplay - 1;
+	int hsize = state->adjusted_mode.crtc_hdisplay - 1;
+	int vsize = state->adjusted_mode.crtc_vdisplay - 1;
+	int sizecfg = hsize | vsize << LCDC_BG_VSIZE;
 
-  int sizecfg = hsize | vsize << LCDC_BG_VSIZE;
-  sf_fb_lcdcwrite32(sf_crtc, LCDC_BACKGROUD, sizecfg);
-  LCDC_PRT("LCDC Dest H-Size: %d, V-Size: %d\n", hsize, vsize);
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_BACKGROUD, sizecfg);
+	LCDC_PRT("LCDC Dest H-Size: %d, V-Size: %d\n", hsize, vsize);
 }
 
 void lcdc_rgb_dclk_cfg(struct starfive_crtc *sf_crtc, int dot_clk_sel)
 {
-  int cfg = dot_clk_sel << 16;
-
-  sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_DCLK, cfg);
+	int cfg = dot_clk_sel << 16;
 
-  LCDC_PRT("LCDC Dot_clock_output_sel: 0x%x\n", cfg);
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_DCLK, cfg);
+	LCDC_PRT("LCDC Dot_clock_output_sel: 0x%x\n", cfg);
 }
 
 
@@ -159,21 +158,21 @@ void lcdc_rgb_dclk_cfg(struct starfive_crtc *sf_crtc, int dot_clk_sel)
 void lcdc_win_cfgA(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state, int winNum, int layEn, int clorTab,
 			int colorEn, int addrMode, int lock)
 {
-   int cfg;
-   int hsize = state->adjusted_mode.crtc_hdisplay - 1;
-   int vsize = state->adjusted_mode.crtc_vdisplay - 1;
-   int srcSel_v = 1;
+	int cfg;
+	int hsize = state->adjusted_mode.crtc_hdisplay - 1;
+	int vsize = state->adjusted_mode.crtc_vdisplay - 1;
+	int srcSel_v = 1;
 
-   if(sf_crtc->pp_conn_lcdc < 0)
+	if (sf_crtc->pp_conn_lcdc < 0)
 		srcSel_v = 0;
 
-   cfg = hsize | vsize << LCDC_WIN_VSIZE | layEn << LCDC_WIN_EN |
-	 clorTab << LCDC_CC_EN | colorEn << LCDC_CK_EN |
-	 srcSel_v << LCDC_WIN_ISSEL | addrMode << LCDC_WIN_PM |
-	 lock << LCDC_WIN_CLK;
+	cfg = hsize | vsize << LCDC_WIN_VSIZE | layEn << LCDC_WIN_EN |
+		clorTab << LCDC_CC_EN | colorEn << LCDC_CK_EN |
+		srcSel_v << LCDC_WIN_ISSEL | addrMode << LCDC_WIN_PM |
+		lock << LCDC_WIN_CLK;
 
-   sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_A + winNum * 0xC, cfg);
-   LCDC_PRT("LCDC Win%d H-Size: %d, V-Size: %d, layEn: %d, Src: %d, AddrMode: %d\n",
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_A + winNum * 0xC, cfg);
+	LCDC_PRT("LCDC Win%d H-Size: %d, V-Size: %d, layEn: %d, Src: %d, AddrMode: %d\n",
 		winNum, hsize, vsize, layEn, srcSel_v, addrMode);
 }
 
@@ -181,17 +180,6 @@ void lcdc_win_cfgA(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state,
 void lcdc_win_cfgB(struct starfive_crtc *sf_crtc, int winNum, int xpos, int ypos, int argbOrd)
 {
 	int win_format = sf_crtc->lcdcfmt;
-/*
-	if(sf_crtc->pp_conn_lcdc < 0) { //ddr -> lcdc
-		win_format = sf_crtc->ddr_format;
-		LCDC_PRT("LCDC win_format: 0x%x\n",win_format);
-	} else { //ddr -> pp -> lcdc
-		win_format = ppfmt_to_lcdcfmt(sf_crtc->pp[sf_crtc->pp_conn_lcdc].dst.format);
-    }
-*/
-	//if(6 == sf_crtc->encoder_type)
-	//	argbOrd=1;
-
 	int cfg = xpos | ypos << LCDC_WIN_VPOS | win_format << LCDC_WIN_FMT
 		       | argbOrd << LCDC_WIN_ARGB_ORDER;
 
@@ -203,8 +191,8 @@ void lcdc_win_cfgB(struct starfive_crtc *sf_crtc, int winNum, int xpos, int ypos
 //? Color key
 void lcdc_win_cfgC(struct starfive_crtc *sf_crtc, int winNum, int colorKey)
 {
-  sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_C + winNum * 0xC, colorKey);
-  LCDC_PRT("LCDC Win%d Color Key: 0x%6x\n", winNum, colorKey);
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_C + winNum * 0xC, colorKey);
+	LCDC_PRT("LCDC Win%d Color Key: 0x%6x\n", winNum, colorKey);
 }
 
 //? hsize
@@ -214,16 +202,52 @@ void lcdc_win_srcSize(struct starfive_crtc *sf_crtc, struct drm_crtc_state *stat
 	int addr, off, winsize, preCfg, cfg;
 	int hsize = state->adjusted_mode.crtc_hdisplay - 1;
 
-	switch(winNum) {
-	case 0 : {addr = LCDC_WIN01_HSIZE; off = 0xfffff000; winsize = hsize; break;}
-	case 1 : {addr = LCDC_WIN01_HSIZE; off = 0xff000fff; winsize = hsize << LCDC_IMG_HSIZE; break;}
-	case 2 : {addr = LCDC_WIN23_HSIZE; off = 0xfffff000; winsize = hsize; break;}
-	case 3 : {addr = LCDC_WIN23_HSIZE; off = 0xff000fff; winsize = hsize << LCDC_IMG_HSIZE; break;}
-	case 4 : {addr = LCDC_WIN45_HSIZE; off = 0xfffff000; winsize = hsize; break;}
-	case 5 : {addr = LCDC_WIN45_HSIZE; off = 0xff000fff; winsize = hsize << LCDC_IMG_HSIZE; break;}
-	case 6 : {addr = LCDC_WIN67_HSIZE; off = 0xfffff000; winsize = hsize; break;}
-	case 7 : {addr = LCDC_WIN67_HSIZE; off = 0xff000fff; winsize = hsize << LCDC_IMG_HSIZE; break;}
-	default: {addr = LCDC_WIN01_HSIZE; off = 0xfffff000; winsize = hsize; break;}
+	switch (winNum) {
+	case 0:
+		addr = LCDC_WIN01_HSIZE;
+		off = 0xfffff000;
+		winsize = hsize;
+		break;
+	case 1:
+		addr = LCDC_WIN01_HSIZE;
+		off = 0xff000fff;
+		winsize = hsize << LCDC_IMG_HSIZE;
+		break;
+	case 2:
+		addr = LCDC_WIN23_HSIZE;
+		off = 0xfffff000;
+		winsize = hsize;
+		break;
+	case 3:
+		addr = LCDC_WIN23_HSIZE;
+		off = 0xff000fff;
+		winsize = hsize << LCDC_IMG_HSIZE;
+		break;
+	case 4:
+		addr = LCDC_WIN45_HSIZE;
+		off = 0xfffff000;
+		winsize = hsize;
+		break;
+	case 5:
+		addr = LCDC_WIN45_HSIZE;
+		off = 0xff000fff;
+		winsize = hsize << LCDC_IMG_HSIZE;
+		break;
+	case 6:
+		addr = LCDC_WIN67_HSIZE;
+		off = 0xfffff000;
+		winsize = hsize;
+		break;
+	case 7:
+		addr = LCDC_WIN67_HSIZE;
+		off = 0xff000fff;
+		winsize = hsize << LCDC_IMG_HSIZE;
+		break;
+	default:
+		addr = LCDC_WIN01_HSIZE;
+		off = 0xfffff000;
+		winsize = hsize;
+		break;
 	}
 	preCfg = sf_fb_lcdcread32(sf_crtc, addr)  & off;
 	cfg = winsize | preCfg;
@@ -239,6 +263,7 @@ void lcdc_alphaVal_cfg(struct starfive_crtc *sf_crtc, int val1, int val2, int va
 			| sel << LCDC_01_ALPHA_SEL;
 
 	int preVal = 0xfffb0000 & sf_fb_lcdcread32(sf_crtc, LCDC_ALPHA_VALUE);
+
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_ALPHA_VALUE, preVal | val);
 	LCDC_PRT("LCDC Alpha 1: %x, 2: %x, 3: %x, 4: %x\n", val1, val2, val3, val4);
 }
@@ -247,22 +272,22 @@ void lcdc_panel_cfg(struct starfive_crtc *sf_crtc, int buswid, int depth, int tx
 		int rgb565sel, int rgb888sel)
 {
 	int cfg = buswid | depth << LCDC_COLOR_DEP
-			  | txcycle << LCDC_TCYCLES
-			  | pixpcycle << LCDC_PIXELS
-			  | rgb565sel << LCDC_565RGB_SEL
-			  | rgb888sel << LCDC_888RGB_SEL;
+			| txcycle << LCDC_TCYCLES
+			| pixpcycle << LCDC_PIXELS
+			| rgb565sel << LCDC_565RGB_SEL
+			| rgb888sel << LCDC_888RGB_SEL;
 
-  sf_fb_lcdcwrite32(sf_crtc, LCDC_PANELDATAFMT, cfg);
-  LCDC_PRT("LCDC bus bit: :%d, pixDep: 0x%x, txCyle: %d, %dpix/cycle, RGB565 2cycle_%d, RGB888 3cycle_%d\n",
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_PANELDATAFMT, cfg);
+	LCDC_PRT("LCDC bus bit: :%d, pixDep: 0x%x, txCyle: %d, %dpix/cycle, RGB565 2cycle_%d, RGB888 3cycle_%d\n",
 		buswid, depth, txcycle, pixpcycle, rgb565sel, rgb888sel);
 }
 
 //winNum: 0-2
 void lcdc_win02Addr_cfg(struct starfive_crtc *sf_crtc, int addr0, int addr1)
 {
-   sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0STARTADDR0 + sf_crtc->winNum * 0x8, addr0);
-   sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0STARTADDR1 + sf_crtc->winNum * 0x8, addr1);
-   LCDC_PRT("LCDC Win%d Start Addr0: 0x%8x, Addr1: 0x%8x\n", sf_crtc->winNum, addr0, addr1);
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0STARTADDR0 + sf_crtc->winNum * 0x8, addr0);
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0STARTADDR1 + sf_crtc->winNum * 0x8, addr1);
+	LCDC_PRT("LCDC Win%d Start Addr0: 0x%8x, Addr1: 0x%8x\n", sf_crtc->winNum, addr0, addr1);
 }
 
 void starfive_set_win_addr(struct starfive_crtc *sf_crtc, int addr)
@@ -274,8 +299,8 @@ EXPORT_SYMBOL(starfive_set_win_addr);
 void lcdc_enable_intr(struct starfive_crtc *sf_crtc)
 {
 	int cfg;
-	cfg = ~(0x1 << LCDC_OUT_FRAME_END);
 
+	cfg = ~(0x1 << LCDC_OUT_FRAME_END);
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_MSK, cfg);
 }
 EXPORT_SYMBOL(lcdc_enable_intr);
@@ -291,8 +316,7 @@ int lcdc_win_sel(struct starfive_crtc *sf_crtc, enum lcdc_in_mode sel)
 {
 	int winNum = 2;
 
-	switch(sel)
-	{
+	switch (sel) {
 	case LCDC_IN_LCD_AXI:
 		winNum = LCDC_WIN_0;
 		break;
@@ -318,30 +342,30 @@ EXPORT_SYMBOL(lcdc_win_sel);
 
 void lcdc_dsi_sel(struct starfive_crtc *sf_crtc)
 {
-  int temp;
-  u32 lcdcEn = 0x1;
-  u32 workMode = 0x1;
-  u32 cfg = lcdcEn | workMode << LCDC_WORK_MODE;
+	int temp;
+	u32 lcdcEn = 0x1;
+	u32 workMode = 0x1;
+	u32 cfg = lcdcEn | workMode << LCDC_WORK_MODE;
 
-  sf_fb_lcdcwrite32(sf_crtc, LCDC_GCTRL, cfg);
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_GCTRL, cfg);
 
-  temp = starfive_lcdc_rstread32(sf_crtc, SRST_ASSERT0);
-  temp &= ~(0x1<<BIT_RST_DSI_DPI_PIX);
-  starfive_lcdc_rstwrite32(sf_crtc, SRST_ASSERT0, temp);
+	temp = starfive_lcdc_rstread32(sf_crtc, SRST_ASSERT0);
+	temp &= ~(0x1<<BIT_RST_DSI_DPI_PIX);
+	starfive_lcdc_rstwrite32(sf_crtc, SRST_ASSERT0, temp);
 }
 EXPORT_SYMBOL(lcdc_dsi_sel);
 
 irqreturn_t lcdc_isr_handler(int this_irq, void *dev_id)
 {
 	struct starfive_crtc *sf_crtc = (struct starfive_crtc *)dev_id;
-	static int count = 0;
+	static int count;
 	u32 intr_status = 0;
 
 	intr_status = sf_fb_lcdcread32(sf_crtc, LCDC_INT_STATUS);
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_CLR, 0xffffffff);
 
-	count ++;
-	if(0 == count % 100)
+	count++;
+	if (count % 100 == 0)
 		LCDC_PRT("lcdc count = %d, intr_status = 0x%x\n", count, intr_status);
 	return IRQ_HANDLED;
 }
@@ -351,7 +375,7 @@ void lcdc_int_cfg(struct starfive_crtc *sf_crtc, int mask)
 {
 	int cfg;
 
-	if(mask==0x1)
+	if (mask == 0x1)
 		cfg = 0xffffffff;
 	else
 		cfg = ~(0x1 << LCDC_OUT_FRAME_END); //only frame end interrupt mask
@@ -366,9 +390,8 @@ void lcdc_config(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state, in
 	lcdc_desize_cfg(sf_crtc, state);
 	lcdc_rgb_dclk_cfg(sf_crtc, 0x1);
 
-	if(sf_crtc->pp_conn_lcdc < 0) { //ddr->lcdc
+	if (sf_crtc->pp_conn_lcdc < 0)
 		lcdc_win02Addr_cfg(sf_crtc, sf_crtc->dma_addr, 0x0);
-	}
 
 	lcdc_win_cfgA(sf_crtc, state, winNum, 0x1, 0x0, 0x0, 0x0, 0x0);
 	lcdc_win_cfgB(sf_crtc, winNum, 0x0, 0x0, 0x0);
@@ -383,6 +406,7 @@ EXPORT_SYMBOL(lcdc_config);
 void lcdc_run(struct starfive_crtc *sf_crtc, uint32_t winMode, uint32_t lcdTrig)
 {
 	uint32_t runcfg = winMode << LCDC_EN_CFG_MODE | lcdTrig;
+
 	sf_fb_lcdcwrite32(sf_crtc, LCDC_SWITCH, runcfg);
 	LCDC_PRT("Start run LCDC\n");
 }
@@ -403,7 +427,8 @@ static int sf_fb_lcdc_clk_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_sta
 	return ret;
 }
 
-static int sf_fb_lcdc_init(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state) {
+static int sf_fb_lcdc_init(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
+{
 	int pp_id;
 	int lcd_in_pp;
 	int winNum;
@@ -428,21 +453,22 @@ static int sf_fb_lcdc_init(struct starfive_crtc *sf_crtc, struct drm_crtc_state
 
 int starfive_lcdc_enable(struct starfive_crtc *sf_crtc)
 {
-	int ret = 0 ;
+	int ret = 0;
 	struct drm_crtc_state *state = sf_crtc->crtc.state;
+
 	lcdc_disable_intr(sf_crtc);
 
 	if (sf_fb_lcdc_clk_cfg(sf_crtc, state)) {
-		dev_err(sf_crtc->dev,"lcdc clock configure fail\n");
+		dev_err(sf_crtc->dev, "lcdc clock configure fail\n");
 		return -EINVAL;
 	}
 
-	// LCDC_PRT("encoder->encoder_type = %d\n",sf_crtc->encoder_type);
-	// if(DRM_MODE_ENCODER_DSI == sf_crtc->encoder_type)//2-TMDS, 3-LVDS, 6-DSI, 8-DPI
-	// 	lcdc_dsi_sel(sf_crtc);
+	//LCDC_PRT("encoder->encoder_type = %d\n",sf_crtc->encoder_type);
+	//if(DRM_MODE_ENCODER_DSI == sf_crtc->encoder_type)//2-TMDS, 3-LVDS, 6-DSI, 8-DPI
+	//	lcdc_dsi_sel(sf_crtc);
 
 	if (sf_fb_lcdc_init(sf_crtc, state)) {
-		dev_err(sf_crtc->dev,"lcdc init fail\n");
+		dev_err(sf_crtc->dev, "lcdc init fail\n");
 		return -EINVAL;
 	}
 
@@ -457,7 +483,6 @@ EXPORT_SYMBOL(starfive_lcdc_enable);
 
 void starfive_lcdc_disable(struct starfive_crtc *sf_crtc)
 {
-	int ret = 0 ;
 	struct drm_crtc_state *state = sf_crtc->crtc.state;
 
 	lcdc_disable_intr(sf_crtc);
diff --git a/drivers/gpu/drm/starfive/starfive_drm_lcdc.h b/drivers/gpu/drm/starfive/starfive_drm_lcdc.h
index 6b124c491272..f71e57435abe 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_lcdc.h
+++ b/drivers/gpu/drm/starfive/starfive_drm_lcdc.h
@@ -11,7 +11,7 @@
 
 #include "starfive_drm_crtc.h"
 
-enum lcdc_in_mode{
+enum lcdc_in_mode {
 	LCDC_IN_LCD_AXI = 0,
 	LCDC_IN_VPP2,
 	LCDC_IN_VPP1,
@@ -19,7 +19,7 @@ enum lcdc_in_mode{
 	LCDC_IN_MAPCONVERT,
 };
 
-enum lcdc_win_num{
+enum lcdc_win_num {
 	LCDC_WIN_0 = 0,
 	LCDC_WIN_1,
 	LCDC_WIN_2,
@@ -28,41 +28,41 @@ enum lcdc_win_num{
 	LCDC_WIN_5,
 };
 
-enum WIN_FMT{
-    WIN_FMT_RGB565 = 4,
-    WIN_FMT_xRGB1555,
-    WIN_FMT_xRGB4444,
-    WIN_FMT_xRGB8888,
+enum WIN_FMT {
+	WIN_FMT_RGB565 = 4,
+	WIN_FMT_xRGB1555,
+	WIN_FMT_xRGB4444,
+	WIN_FMT_xRGB8888,
 };
 
 #define LCDC_STOP	0
 #define LCDC_RUN	1
 
 //lcdc registers
-#define LCDC_SWITCH		0x0000
-#define LCDC_GCTRL		0x0004
-#define LCDC_INT_STATUS		0x0008
-#define LCDC_INT_MSK		0x000C
-#define LCDC_INT_CLR		0x0010
-#define LCDC_RGB_H_TMG		0x0014
-#define LCDC_RGB_V_TMG		0x0018
-#define LCDC_RGB_W_TMG		0x001C
-#define LCDC_RGB_DCLK		0x0020
-#define LCDC_M_CS_CTRL		0x0024
+#define LCDC_SWITCH				0x0000
+#define LCDC_GCTRL				0x0004
+#define LCDC_INT_STATUS			0x0008
+#define LCDC_INT_MSK			0x000C
+#define LCDC_INT_CLR			0x0010
+#define LCDC_RGB_H_TMG			0x0014
+#define LCDC_RGB_V_TMG			0x0018
+#define LCDC_RGB_W_TMG			0x001C
+#define LCDC_RGB_DCLK			0x0020
+#define LCDC_M_CS_CTRL			0x0024
 #define LCDC_DeltaRGB_CFG		0x0028
-#define LCDC_BACKGROUD		0x002C
-#define LCDC_WIN0_CFG_A		0x0030
-#define LCDC_WIN0_CFG_B		0x0034
-#define LCDC_WIN0_CFG_C		0x0038
-#define LCDC_WIN1_CFG_A		0x003C
-#define LCDC_WIN1_CFG_B		0x0040
-#define LCDC_WIN1_CFG_C		0x0044
-#define LCDC_WIN2_CFG_A		0x0048
-#define LCDC_WIN2_CFG_B		0x004C
-#define LCDC_WIN2_CFG_C		0x0050
-#define LCDC_WIN3_CFG_A		0x0054
-#define LCDC_WIN3_CFG_B		0x0058
-#define LCDC_WIN3_CFG_C		0x005C
+#define LCDC_BACKGROUD			0x002C
+#define LCDC_WIN0_CFG_A			0x0030
+#define LCDC_WIN0_CFG_B			0x0034
+#define LCDC_WIN0_CFG_C			0x0038
+#define LCDC_WIN1_CFG_A			0x003C
+#define LCDC_WIN1_CFG_B			0x0040
+#define LCDC_WIN1_CFG_C			0x0044
+#define LCDC_WIN2_CFG_A			0x0048
+#define LCDC_WIN2_CFG_B			0x004C
+#define LCDC_WIN2_CFG_C			0x0050
+#define LCDC_WIN3_CFG_A			0x0054
+#define LCDC_WIN3_CFG_B			0x0058
+#define LCDC_WIN3_CFG_C			0x005C
 #define LCDC_WIN01_HSIZE		0x0090
 #define LCDC_WIN23_HSIZE		0x0094
 #define LCDC_WIN45_HSIZE		0x0098
@@ -76,75 +76,75 @@ enum WIN_FMT{
 /* Definition controller bit for LCDC registers */
 //for LCDC_SWITCH
 #define LCDC_DTRANS_SWITCH		0
-#define LCDC_MPU_START		1
+#define LCDC_MPU_START			1
 #define LCDC_EN_CFG_MODE		2
 //for LCDC_GCTRL
-#define LCDC_EN		0
-#define LCDC_WORK_MODE		1
-#define LCDC_A0_P		4
-#define LCDC_ENABLE_P		5
-#define LCDC_DOTCLK_P		6
-#define LCDC_HSYNC_P		7
-#define LCDC_VSYNC_P		8
-#define LCDC_DITHER_EN		9
-#define LCDC_R2Y_BPS		10
-#define LCDC_MS_SEL		11
+#define LCDC_EN					0
+#define LCDC_WORK_MODE			1
+#define LCDC_A0_P				4
+#define LCDC_ENABLE_P			5
+#define LCDC_DOTCLK_P			6
+#define LCDC_HSYNC_P			7
+#define LCDC_VSYNC_P			8
+#define LCDC_DITHER_EN			9
+#define LCDC_R2Y_BPS			10
+#define LCDC_MS_SEL				11
 #define LCDC_TV_LCD_PATHSEL		12
-#define LCDC_INTERLACE		13
-#define LCDC_CBCR_ORDER		14
-#define LCDC_INT_SEL		15
-#define LCDC_INT_FREQ		24
+#define LCDC_INTERLACE			13
+#define LCDC_CBCR_ORDER			14
+#define LCDC_INT_SEL			15
+#define LCDC_INT_FREQ			24
 //for LCDC_INT_MSK
 #define LCDC_OUT_FRAME_END		5
 //for RGB_H_TMG,RGB_V_TMG,RGB_W_TMG
-#define LCDC_RGB_HBK		0
-#define LCDC_RGB_HFP		16
-#define LCDC_RGB_VBK		0
-#define LCDC_RGB_VFP		16
-#define LCDC_RGB_HPW		0
-#define LCDC_RGB_VPW		8
-#define LCDC_RGB_UNIT		16
+#define LCDC_RGB_HBK			0
+#define LCDC_RGB_HFP			16
+#define LCDC_RGB_VBK			0
+#define LCDC_RGB_VFP			16
+#define LCDC_RGB_HPW			0
+#define LCDC_RGB_VPW			8
+#define LCDC_RGB_UNIT			16
 //for BACKGROUD
-#define LCDC_BG_HSIZE		0
-#define LCDC_BG_VSIZE		12
+#define LCDC_BG_HSIZE			0
+#define LCDC_BG_VSIZE			12
 //for WINx_CFG_A/B/C
-#define LCDC_WIN_HSIZE		0
-#define LCDC_WIN_VSIZE		12
-#define LCDC_WIN_EN		24
-#define LCDC_CC_EN		25
-#define LCDC_CK_EN		26
-#define LCDC_WIN_ISSEL		27
-#define LCDC_WIN_PM		28
-#define LCDC_WIN_CLK		30
-#define LCDC_WIN_HPOS		0
-#define LCDC_WIN_VPOS		12
-#define LCDC_WIN_FMT		24
+#define LCDC_WIN_HSIZE			0
+#define LCDC_WIN_VSIZE			12
+#define LCDC_WIN_EN				24
+#define LCDC_CC_EN				25
+#define LCDC_CK_EN				26
+#define LCDC_WIN_ISSEL			27
+#define LCDC_WIN_PM				28
+#define LCDC_WIN_CLK			30
+#define LCDC_WIN_HPOS			0
+#define LCDC_WIN_VPOS			12
+#define LCDC_WIN_FMT			24
 #define LCDC_WIN_ARGB_ORDER		27
-#define LCDC_WIN_CC		0
+#define LCDC_WIN_CC				0
 //for WINxx_HSIZE
-#define LCDC_IMG_HSIZE		12
+#define LCDC_IMG_HSIZE			12
 //for LCDC_ALPHA_VALUE
-#define LCDC_ALPHA1		0
-#define LCDC_ALPHA2		4
-#define LCDC_ALPHA3		8
-#define LCDC_ALPHA4		12
+#define LCDC_ALPHA1				0
+#define LCDC_ALPHA2				4
+#define LCDC_ALPHA3				8
+#define LCDC_ALPHA4				12
 #define LCDC_A_GLBL_ALPHA		16
 #define LCDC_B_GLBL_ALPHA		17
 #define LCDC_01_ALPHA_SEL		18
 //for LCDC_PANELDATAFMT
-#define LCDC_BUS_W		0
-#define LCDC_TCYCLES		2
-#define LCDC_COLOR_DEP		4
-#define LCDC_PIXELS		7
-#define LCDC_332RGB_SEL		8
-#define LCDC_444RGB_SEL		9
-#define LCDC_666RGB_SEL		12
-#define LCDC_565RGB_SEL		16
-#define LCDC_888RGB_SEL		18
+#define LCDC_BUS_W				0
+#define LCDC_TCYCLES			2
+#define LCDC_COLOR_DEP			4
+#define LCDC_PIXELS				7
+#define LCDC_332RGB_SEL			8
+#define LCDC_444RGB_SEL			9
+#define LCDC_666RGB_SEL			12
+#define LCDC_565RGB_SEL			16
+#define LCDC_888RGB_SEL			18
 
 //sysrst registers
-#define SRST_ASSERT0	    0x00
-#define SRST_STATUS0    	0x04
+#define SRST_ASSERT0		0x00
+#define SRST_STATUS0		0x04
 /* Definition controller bit for syd rst registers */
 #define BIT_RST_DSI_DPI_PIX		17
 
diff --git a/drivers/gpu/drm/starfive/starfive_drm_plane.c b/drivers/gpu/drm/starfive/starfive_drm_plane.c
index e0d44a4a4a00..84b923849842 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_plane.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_plane.c
@@ -1,211 +1,205 @@
-// SPDX-License-Identifier: GPL-2.0-only

-/*

- * Copyright (c) 2021 StarFive Technology Co., Ltd

- * Author: StarFive <StarFive@starfivetech.com>

- */

-

-#include <drm/drm.h>

-#include <drm/drm_atomic.h>

-#include <drm/drm_atomic_helper.h>

-#include <drm/drm_fourcc.h>

-#include <drm/drm_atomic_uapi.h>

-#include <drm/drm_plane_helper.h>

-#include <drm/drm_gem_framebuffer_helper.h>

-

-#include "starfive_drm_crtc.h"

-#include "starfive_drm_plane.h"

-#include "starfive_drm_gem.h"

-#include "starfive_drm_lcdc.h"

-#include "starfive_drm_vpp.h"

-

-static const u32 formats[] = {

-	DRM_FORMAT_RGB565,

-	DRM_FORMAT_UYVY,

-	DRM_FORMAT_VYUY,

-	DRM_FORMAT_YUYV,

-	DRM_FORMAT_YVYU,

-

-	DRM_FORMAT_YUV420,

-	DRM_FORMAT_NV21,

-	DRM_FORMAT_NV12,

-

-	DRM_FORMAT_ARGB8888,

-	DRM_FORMAT_ABGR8888,

-};

-

-static void starfive_plane_destroy(struct drm_plane *plane)

-{

-	drm_plane_cleanup(plane);

-}

-

-static const struct drm_plane_funcs starfive_plane_funcs = {

-	.update_plane = drm_atomic_helper_update_plane,

-	.disable_plane = drm_atomic_helper_disable_plane,

-	.destroy = starfive_plane_destroy,

-	.set_property = NULL,

-	.reset = drm_atomic_helper_plane_reset,

-	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,

-	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,

-};

-

-static void starfive_plane_atomic_disable(struct drm_plane *plane,

-				     struct drm_plane_state *old_state)

-{

-}

-

-static int starfive_plane_atomic_check(struct drm_plane *plane,

-			   struct drm_plane_state *state)

-{

-	struct drm_framebuffer *fb = state->fb;

-	struct drm_crtc_state *crtc_state;

-	int ret;

-

-	if (!fb) {

-		return 0;

-	}

-

-	if (WARN_ON(!state->crtc)) {

-		return 0;

-	}

-

-	/*ret = starfive_drm_plane_check(state->crtc, plane,

-				       to_starfive_plane_state(state));

-	if (ret)

-		return ret;*/

-

-	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);

-	if (IS_ERR(crtc_state))

-		return PTR_ERR(crtc_state);

-

-	return drm_atomic_helper_check_plane_state(state, crtc_state,

-						   DRM_PLANE_HELPER_NO_SCALING,

-						   DRM_PLANE_HELPER_NO_SCALING,

-						   true, true);

-}

-

-static void starfive_plane_atomic_update(struct drm_plane *plane,

-	   struct drm_plane_state *old_state)

-{

-	struct drm_plane_state *state = plane->state;

-	struct drm_crtc *crtc = state->crtc;

-	struct drm_framebuffer *fb = state->fb;

-

-	dma_addr_t dma_addr;

-	struct drm_gem_object *obj;

-	struct starfive_drm_gem_obj *starfive_obj;

-	unsigned int pitch, format;

-

-	struct starfive_crtc *sf_crtc = to_starfive_crtc(crtc);

-

-	if (!crtc || WARN_ON(!fb))

-		return;

-

-	if (!plane->state->visible) {

-		starfive_plane_atomic_disable(plane, old_state);

-		return;

-	}

-

-	obj = fb->obj[0];

-	starfive_obj = to_starfive_gem_obj(obj);

-	dma_addr = starfive_obj->dma_addr;

-	pitch = fb->pitches[0];

-	format = fb->format->format;

-

-	dma_addr += (plane->state->src.x1 >> 16) * fb->format->cpp[0];

-	dma_addr += (plane->state->src.y1 >> 16) * pitch;

-	if(sf_crtc->ddr_format != format){

-		sf_crtc->ddr_format = format;

-		sf_crtc->ddr_format_change = true;

-	}

-	else

-		sf_crtc->ddr_format_change = false;

-

-	if(sf_crtc->dma_addr != dma_addr){

-		sf_crtc->dma_addr = dma_addr;

-		sf_crtc->dma_addr_change = true;

-	}

-	else

-		sf_crtc->dma_addr_change = false;

-

-}

-

-static int starfive_plane_atomic_async_check(struct drm_plane *plane,

-				   struct drm_plane_state *state)

-{

-	struct drm_crtc_state *crtc_state;

-

-	if (plane != state->crtc->cursor) {

-		return -EINVAL;

-	}

-

-	if (!plane->state) {

-		return -EINVAL;

-	}

-

-	if (!plane->state->fb) {

-		return -EINVAL;

-	}

-

-	if (state->state)

-	   crtc_state = drm_atomic_get_existing_crtc_state(state->state,

-							   state->crtc);

-	else /* Special case for asynchronous cursor updates. */

-	   crtc_state = state->crtc->state;

-

-	return drm_atomic_helper_check_plane_state(plane->state, crtc_state,

-						  DRM_PLANE_HELPER_NO_SCALING,

-						  DRM_PLANE_HELPER_NO_SCALING,

-						  true, true);

-

-}

-

-static void starfive_plane_atomic_async_update(struct drm_plane *plane,

-					 struct drm_plane_state *new_state)

-{

-	struct starfive_crtc *crtcp = to_starfive_crtc(plane->state->crtc);

-	struct drm_framebuffer *old_fb = plane->state->fb;

-

-	plane->state->crtc_x = new_state->crtc_x;

-	plane->state->crtc_y = new_state->crtc_y;

-	plane->state->crtc_h = new_state->crtc_h;

-	plane->state->crtc_w = new_state->crtc_w;

-	plane->state->src_x = new_state->src_x;

-	plane->state->src_y = new_state->src_y;

-	plane->state->src_h = new_state->src_h;

-	plane->state->src_w = new_state->src_w;

-	swap(plane->state->fb, new_state->fb);

-

-	if (crtcp->is_enabled) {

-		starfive_plane_atomic_update(plane, plane->state);

-		spin_lock(&crtcp->reg_lock);

-		starfive_crtc_hw_config_simple(crtcp);

-		spin_unlock(&crtcp->reg_lock);

-	}

-}

-

-static const struct drm_plane_helper_funcs starfive_plane_helper_funcs = {

-	.atomic_check = starfive_plane_atomic_check,

-	.atomic_update = starfive_plane_atomic_update,

-	.prepare_fb = drm_gem_fb_prepare_fb,

-	.atomic_disable = starfive_plane_atomic_disable,

-	.atomic_async_check = starfive_plane_atomic_async_check,

-	.atomic_async_update = starfive_plane_atomic_async_update,

-};

-

-int starfive_plane_init(struct drm_device *dev, struct starfive_crtc *starfive_crtc,

-						enum drm_plane_type type)

-{

-	int ret;

-    int i;

-	ret = drm_universal_plane_init(dev, starfive_crtc->planes, 0,

-				       &starfive_plane_funcs, formats,

-				       ARRAY_SIZE(formats), NULL, type, NULL);

-	if (ret) {

-		dev_err(dev->dev,"failed to initialize plane\n");

-		return ret;

-	}

-

-	drm_plane_helper_add(starfive_crtc->planes, &starfive_plane_helper_funcs);

-

-	return 0;

-}

+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 StarFive Technology Co., Ltd
+ * Author: StarFive <StarFive@starfivetech.com>
+ */
+
+#include <drm/drm.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_atomic_uapi.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+
+#include "starfive_drm_crtc.h"
+#include "starfive_drm_plane.h"
+#include "starfive_drm_gem.h"
+#include "starfive_drm_lcdc.h"
+#include "starfive_drm_vpp.h"
+
+static const u32 formats[] = {
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+
+	DRM_FORMAT_YUV420,
+	DRM_FORMAT_NV21,
+	DRM_FORMAT_NV12,
+
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+};
+
+static void starfive_plane_destroy(struct drm_plane *plane)
+{
+	drm_plane_cleanup(plane);
+}
+
+static const struct drm_plane_funcs starfive_plane_funcs = {
+	.update_plane = drm_atomic_helper_update_plane,
+	.disable_plane = drm_atomic_helper_disable_plane,
+	.destroy = starfive_plane_destroy,
+	.set_property = NULL,
+	.reset = drm_atomic_helper_plane_reset,
+	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static void starfive_plane_atomic_disable(struct drm_plane *plane,
+				     struct drm_plane_state *old_state)
+{
+}
+
+static int starfive_plane_atomic_check(struct drm_plane *plane,
+			   struct drm_plane_state *state)
+{
+	struct drm_framebuffer *fb = state->fb;
+	struct drm_crtc_state *crtc_state;
+	int ret;
+
+	if (!fb)
+		return 0;
+
+	if (WARN_ON(!state->crtc))
+		return 0;
+
+	/*ret = starfive_drm_plane_check(state->crtc, plane,
+				       to_starfive_plane_state(state));
+	if (ret)
+		return ret;*/
+
+	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
+	if (IS_ERR(crtc_state))
+		return PTR_ERR(crtc_state);
+
+	return drm_atomic_helper_check_plane_state(state, crtc_state,
+						   DRM_PLANE_HELPER_NO_SCALING,
+						   DRM_PLANE_HELPER_NO_SCALING,
+						   true, true);
+}
+
+static void starfive_plane_atomic_update(struct drm_plane *plane,
+	   struct drm_plane_state *old_state)
+{
+	struct drm_plane_state *state = plane->state;
+	struct drm_crtc *crtc = state->crtc;
+	struct drm_framebuffer *fb = state->fb;
+
+	dma_addr_t dma_addr;
+	struct drm_gem_object *obj;
+	struct starfive_drm_gem_obj *starfive_obj;
+	unsigned int pitch, format;
+
+	struct starfive_crtc *sf_crtc = to_starfive_crtc(crtc);
+
+	if (!crtc || WARN_ON(!fb))
+		return;
+
+	if (!plane->state->visible) {
+		starfive_plane_atomic_disable(plane, old_state);
+		return;
+	}
+
+	obj = fb->obj[0];
+	starfive_obj = to_starfive_gem_obj(obj);
+	dma_addr = starfive_obj->dma_addr;
+	pitch = fb->pitches[0];
+	format = fb->format->format;
+
+	dma_addr += (plane->state->src.x1 >> 16) * fb->format->cpp[0];
+	dma_addr += (plane->state->src.y1 >> 16) * pitch;
+	if (sf_crtc->ddr_format != format) {
+		sf_crtc->ddr_format = format;
+		sf_crtc->ddr_format_change = true;
+	} else
+		sf_crtc->ddr_format_change = false;
+
+	if (sf_crtc->dma_addr != dma_addr) {
+		sf_crtc->dma_addr = dma_addr;
+		sf_crtc->dma_addr_change = true;
+	} else
+		sf_crtc->dma_addr_change = false;
+
+}
+
+static int starfive_plane_atomic_async_check(struct drm_plane *plane,
+				   struct drm_plane_state *state)
+{
+	struct drm_crtc_state *crtc_state;
+
+	if (plane != state->crtc->cursor)
+		return -EINVAL;
+
+	if (!plane->state)
+		return -EINVAL;
+
+	if (!plane->state->fb)
+		return -EINVAL;
+
+	if (state->state)
+		crtc_state = drm_atomic_get_existing_crtc_state(state->state,
+							   state->crtc);
+	else /* Special case for asynchronous cursor updates. */
+		crtc_state = state->crtc->state;
+
+	return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
+						DRM_PLANE_HELPER_NO_SCALING,
+						DRM_PLANE_HELPER_NO_SCALING,
+						true, true);
+
+}
+
+static void starfive_plane_atomic_async_update(struct drm_plane *plane,
+					 struct drm_plane_state *new_state)
+{
+	struct starfive_crtc *crtcp = to_starfive_crtc(plane->state->crtc);
+	struct drm_framebuffer *old_fb = plane->state->fb;
+
+	plane->state->crtc_x = new_state->crtc_x;
+	plane->state->crtc_y = new_state->crtc_y;
+	plane->state->crtc_h = new_state->crtc_h;
+	plane->state->crtc_w = new_state->crtc_w;
+	plane->state->src_x = new_state->src_x;
+	plane->state->src_y = new_state->src_y;
+	plane->state->src_h = new_state->src_h;
+	plane->state->src_w = new_state->src_w;
+	swap(plane->state->fb, new_state->fb);
+
+	if (crtcp->is_enabled) {
+		starfive_plane_atomic_update(plane, plane->state);
+		spin_lock(&crtcp->reg_lock);
+		starfive_crtc_hw_config_simple(crtcp);
+		spin_unlock(&crtcp->reg_lock);
+	}
+}
+
+static const struct drm_plane_helper_funcs starfive_plane_helper_funcs = {
+	.atomic_check = starfive_plane_atomic_check,
+	.atomic_update = starfive_plane_atomic_update,
+	.prepare_fb = drm_gem_fb_prepare_fb,
+	.atomic_disable = starfive_plane_atomic_disable,
+	.atomic_async_check = starfive_plane_atomic_async_check,
+	.atomic_async_update = starfive_plane_atomic_async_update,
+};
+
+int starfive_plane_init(struct drm_device *dev, struct starfive_crtc *starfive_crtc,
+						enum drm_plane_type type)
+{
+	int ret;
+	int i;
+
+	ret = drm_universal_plane_init(dev, starfive_crtc->planes, 0,
+				       &starfive_plane_funcs, formats,
+				       ARRAY_SIZE(formats), NULL, type, NULL);
+	if (ret) {
+		dev_err(dev->dev, "failed to initialize plane\n");
+		return ret;
+	}
+
+	drm_plane_helper_add(starfive_crtc->planes, &starfive_plane_helper_funcs);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/starfive/starfive_drm_plane.h b/drivers/gpu/drm/starfive/starfive_drm_plane.h
index c989dc42e82c..0fc1ea53803f 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_plane.h
+++ b/drivers/gpu/drm/starfive/starfive_drm_plane.h
@@ -1,12 +1,12 @@
-/* SPDX-License-Identifier: GPL-2.0-only */

-/*

- * Copyright (c) 2021 StarFive Technology Co., Ltd

- * Author: StarFive <StarFive@starfivetech.com>

- */

-

-#ifndef _STARFIVE_DRM_PLANE_H

-#define _STARFIVE_DRM_PLANE_H

-

-int starfive_plane_init(struct drm_device *dev, struct starfive_crtc *starfive_crtc,

-						enum drm_plane_type type);

-#endif /* _STARFIVE_DRM_PLANE_H */

+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 StarFive Technology Co., Ltd
+ * Author: StarFive <StarFive@starfivetech.com>
+ */
+
+#ifndef _STARFIVE_DRM_PLANE_H
+#define _STARFIVE_DRM_PLANE_H
+
+int starfive_plane_init(struct drm_device *dev, struct starfive_crtc *starfive_crtc,
+						enum drm_plane_type type);
+#endif /* _STARFIVE_DRM_PLANE_H */
diff --git a/drivers/gpu/drm/starfive/starfive_drm_seeedpanel.c b/drivers/gpu/drm/starfive/starfive_drm_seeedpanel.c
index d9e98aeb7d6d..3fe44e986bc2 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_seeedpanel.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_seeedpanel.c
@@ -39,25 +39,25 @@
 
 /* I2C registers of the Atmel microcontroller. */
 enum REG_ADDR {
-    REG_ID = 0x80,
-    REG_PORTA, /* BIT(2) for horizontal flip, BIT(3) for vertical flip */
-    REG_PORTB,
-    REG_PORTC,
-    REG_PORTD,
-    REG_POWERON,
-    REG_PWM,
-    REG_DDRA,
-    REG_DDRB,
-    REG_DDRC,
-    REG_DDRD,
-    REG_TEST,
-    REG_WR_ADDRL,
-    REG_WR_ADDRH,
-    REG_READH,
-    REG_READL,
-    REG_WRITEH,
-    REG_WRITEL,
-    REG_ID2,
+	REG_ID = 0x80,
+	REG_PORTA, /* BIT(2) for horizontal flip, BIT(3) for vertical flip */
+	REG_PORTB,
+	REG_PORTC,
+	REG_PORTD,
+	REG_POWERON,
+	REG_PWM,
+	REG_DDRA,
+	REG_DDRB,
+	REG_DDRC,
+	REG_DDRD,
+	REG_TEST,
+	REG_WR_ADDRL,
+	REG_WR_ADDRH,
+	REG_READH,
+	REG_READL,
+	REG_WRITEH,
+	REG_WRITEL,
+	REG_ID2,
 };
 
 /* DSI D-PHY Layer Registers */
@@ -174,8 +174,7 @@ struct seeed_panel_dev {
 	struct mipi_dsi_device *dsi;
 
 	struct device   *dev;
-	int 			irq;
-
+	int			irq;
 };
 
 #if 0
@@ -204,9 +203,9 @@ static void seeed_panel_i2c_write(struct i2c_client *client, u8 reg, u8 val)
 {
 	int ret;
 
-	do{
+	do {
 		ret = i2c_smbus_write_byte_data(client, reg, val);
-	}while(ret);
+	} while (ret);
 
 	if (ret)
 		printk("I2C write failed: %d\n", ret);
@@ -233,9 +232,8 @@ static int seeed_panel_i2c_read(struct i2c_client *client, u8 reg, u8 *val)
 	msg[1].len = 1;
 
 	ret = i2c_transfer(client->adapter, msg, 2);
-	if (ret >= 0) {
+	if (ret >= 0)
 		return 0;
-	}
 
 	return ret;
 }
@@ -249,14 +247,14 @@ static int seeed_panel_i2c_read(struct i2c_client *client, u8 reg, u8 *val)
 
 
 enum dsi_rgb_pattern_t {
-    RGB_PAT_WHITE,
-    RGB_PAT_BLACK,
-    RGB_PAT_RED,
-    RGB_PAT_GREEN,
-    RGB_PAT_BLUE,
-    RGB_PAT_HORIZ_COLORBAR,
-    RGB_PAT_VERT_COLORBAR,
-    RGB_PAT_NUM
+	RGB_PAT_WHITE,
+	RGB_PAT_BLACK,
+	RGB_PAT_RED,
+	RGB_PAT_GREEN,
+	RGB_PAT_BLUE,
+	RGB_PAT_HORIZ_COLORBAR,
+	RGB_PAT_VERT_COLORBAR,
+	RGB_PAT_NUM
 };
 
 static struct seeed_panel_dev *panel_to_seeed(struct drm_panel *panel)
@@ -295,31 +293,17 @@ t_delta_vfp_last(DSI - DPI):	0.00ns (0.00% dsi line)
 */
 
 static const struct drm_display_mode seeed_panel_modes[] = {
-	#ifdef USE_OLD_SCREEN  //seeed panel
-	{
-		.clock = 27500000/1000,
-		.hdisplay = 800,
-		.hsync_start = 800 + 50,
-		.hsync_end = 800 + 50 + 20,
-		.htotal = 800 + 50 + 20+ 10,
-		.vdisplay = 480,
-		.vsync_start = 480 + 135,
-		.vsync_end = 480 + 135 + 5,
-		.vtotal = 480 + 135 + 5 + 5,
-	},
-	#else
 	{
 		.clock = 27000000 / 1000,
 		.hdisplay = 800,
 		.hsync_start = 800 + 90,
 		.hsync_end = 800 + 90 + 5,
-		.htotal = 800 + 90 + 5+ 5,
+		.htotal = 800 + 90 + 5 + 5,
 		.vdisplay = 480,
 		.vsync_start = 480 + 10,
 		.vsync_end = 480 + 10 + 5,
 		.vtotal = 480 + 10 + 5 + 5,
 	},
-	#endif
 };
 
 static int seeed_dsi_write(struct drm_panel *panel, u16 reg, u32 val)
@@ -345,6 +329,7 @@ static void dump_seeed_panel(struct drm_panel *panel)
 	struct seeed_panel_dev *sp = panel_to_seeed(panel);
 	int addr = 0;
 	u8 reg_value = 0;
+
 	for (addr = REG_ID; addr <= REG_ID2; addr++) {
 		seeed_panel_i2c_read(sp->client, addr, &reg_value);
 		printk("addr = 0x%x, val = 0x%x\n", addr, reg_value);
@@ -382,10 +367,10 @@ static int seeed_panel_enable(struct drm_panel *panel)
 	seeed_panel_i2c_write(sp->client, REG_POWERON, 1);
 	udelay(5000);
 	/* Wait for nPWRDWN to go low to indicate poweron is done. */
-    for (i = 0; i < 100; i++) {
+	for (i = 0; i < 100; i++) {
 		seeed_panel_i2c_read(sp->client, REG_PORTB, &reg_value);
-        if (reg_value & 1)
-            break;
+		if (reg_value & 1)
+			break;
     }
 
 	seeed_dsi_write(panel, DSI_LANEENABLE,
@@ -497,27 +482,18 @@ static int seeed_panel_probe(struct i2c_client *client, const struct i2c_device_
 
 	seeed_panel_i2c_read(client, REG_ID, &reg_value);
 	switch (reg_value) {
-		case 0xde: /* ver 1 */
-		case 0xc3: /* ver 2 */
+	case 0xde: /* ver 1 */
+	case 0xc3: /* ver 2 */
 		break;
 
-		default:
-			dev_err(&client->dev, "Unknown Atmel firmware revision: 0x%02x\n", reg_value);
-			//return -ENODEV;
+	default:
+		dev_err(&client->dev, "Unknown Atmel firmware revision: 0x%02x\n", reg_value);
+		//return -ENODEV;
 	}
 
 	seeed_panel_i2c_write(client, REG_PWM, 0);
     seeed_panel_i2c_write(client, REG_POWERON, 0);
 	udelay(1);
-#if 0
-    mdelay(5);
-    /* Wait for nPWRDWN to go low to indicate poweron is done. */
-    for (i = 0; i < 100; i++) {
-		seeed_panel_i2c_read(client, REG_PORTB, &reg_value);
-        if (reg_value & 1)
-            break;
-    }
-#endif
 
 	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
 	if (!endpoint)
@@ -590,7 +566,7 @@ static struct i2c_driver seeed_panel_driver = {
 	.driver = {
 		.owner	= THIS_MODULE,
 		.name	= "seeed_panel",
-        .of_match_table = seeed_panel_dt_ids,
+		.of_match_table = seeed_panel_dt_ids,
 	},
 	.probe		= seeed_panel_probe,
 	.remove		= seeed_panel_remove,
@@ -622,13 +598,9 @@ static struct mipi_dsi_driver seeed_dsi_driver = {
 int init_seeed_panel(void)
 {
 	printk("-----%s: %d\n", __func__, __LINE__);
-    int err;
 	mipi_dsi_driver_register(&seeed_dsi_driver);
 
-	err = i2c_add_driver(&seeed_panel_driver);
-    if (err != 0)
-		printk("i2c driver registration failed, error=%d\n", err);
-	return err;
+	return i2c_add_driver(&seeed_panel_driver);
 }
 EXPORT_SYMBOL(init_seeed_panel);
 
diff --git a/drivers/gpu/drm/starfive/starfive_drm_vpp.c b/drivers/gpu/drm/starfive/starfive_drm_vpp.c
index 14317822d74e..56e1b3af7ab0 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_vpp.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.c
@@ -1,18 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /* driver/video/starfive/starfive_vpp.c
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License version 2 as
-** published by the Free Software Foundation.
-**
-** Copyright (C) 2020 StarFive, Inc.
-**
-** PURPOSE:	This files contains the driver of VPP.
-**
-** CHANGE HISTORY:
-**	Version		Date		Author		Description
-**	0.1.0		2020-10-09	starfive		created
-**
-*/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (C) 2020 StarFive, Inc.
+ *
+ * PURPOSE:	This files contains the driver of VPP.
+ *
+ * CHANGE HISTORY:
+ *	Version		Date		Author		Description
+ *	0.1.0		2020-10-09	starfive		created
+ *
+ */
 
 #include <linux/module.h>
 #include <video/starfive_fb.h>
@@ -27,26 +28,28 @@
 	#define PP_INFO(format, args...) printk(KERN_INFO "[pp]: " format, ## args)
 	#define PP_ERR(format, args...) printk(KERN_ERR "[pp]: " format, ## args)
 #else
-	#define PP_PRT(x...)  do{} while(0)
-	#define PP_INFO(x...)  do{} while(0)
-	#define PP_ERR(x...)  do{} while(0)
+	#define PP_PRT(x...)  do {} while (0)
+	#define PP_INFO(x...)  do {} while (0)
+	#define PP_ERR(x...)  do {} while (0)
 #endif
 
-static inline void sf_set_clear(void __iomem	*addr, u32 reg, u32 set, u32 clear)
+static inline void sf_set_clear(void __iomem *addr, u32 reg, u32 set, u32 clear)
 {
-    u32 value = ioread32(addr+reg);
-    value &= ~clear;
-    value |= set;
-    iowrite32(value,addr+reg);
+	u32 value = ioread32(addr + reg);
+
+	value &= ~clear;
+	value |= set;
+	iowrite32(value, addr + reg);
 }
 
-static inline void sf_reg_status_wait(void __iomem	*addr, u32 reg, u8 offset, u8 value)
+static inline void sf_reg_status_wait(void __iomem *addr, u32 reg, u8 offset, u8 value)
 {
 	u32 temp;
+
 	do {
-		temp = ioread32(addr+reg)>>offset;
+		temp = ioread32(addr + reg) >> offset;
 		temp &= 0x01;
-	} while(temp!=value);
+	} while (temp != value);
 }
 
 static u32 sf_fb_sysread32(struct starfive_crtc *sf_crtc, u32 reg)
@@ -61,35 +64,37 @@ static void sf_fb_syswrite32(struct starfive_crtc *sf_crtc, u32 reg, u32 val)
 
 static u32 sf_fb_vppread32(struct starfive_crtc *sf_crtc, int ppNum, u32 reg)
 {
-	void __iomem	*base_vpp = 0;
-	switch(ppNum) {
-		case 0 :
-			base_vpp = sf_crtc->base_vpp0;
-			break;
-		case 1 :
-			base_vpp = sf_crtc->base_vpp1;
-			break;
-		case 2 :
-			base_vpp = sf_crtc->base_vpp2;
-			break;
-		default:
-			PP_ERR("Err：invalid vpp Number!\n");
-			break;
+	void __iomem *base_vpp = 0;
+
+	switch (ppNum) {
+	case 0:
+		base_vpp = sf_crtc->base_vpp0;
+		break;
+	case 1:
+		base_vpp = sf_crtc->base_vpp1;
+		break;
+	case 2:
+		base_vpp = sf_crtc->base_vpp2;
+		break;
+	default:
+		PP_ERR("Err：invalid vpp Number!\n");
+		break;
 	}
 	return ioread32(base_vpp + reg);
 }
 
 static void sf_fb_vppwrite32(struct starfive_crtc *sf_crtc, int ppNum, u32 reg, u32 val)
 {
-	void __iomem	*base_vpp = 0;
-	switch(ppNum) {
-	case 0 :
+	void __iomem *base_vpp = 0;
+
+	switch (ppNum) {
+	case 0:
 		base_vpp = sf_crtc->base_vpp0;
 		break;
-	case 1 :
+	case 1:
 		base_vpp = sf_crtc->base_vpp1;
 		break;
-	case 2 :
+	case 2:
 		base_vpp = sf_crtc->base_vpp2;
 		break;
 	default:
@@ -102,6 +107,7 @@ static void sf_fb_vppwrite32(struct starfive_crtc *sf_crtc, int ppNum, u32 reg,
 void mapconv_pp0_sel(struct starfive_crtc *sf_crtc, int sel)
 {
 	u32 temp;
+
 	temp = sf_fb_sysread32(sf_crtc, SYS_MAP_CONV);
 	temp &= ~(0x1);
 	temp |= (sel & 0x1);
@@ -112,10 +118,10 @@ EXPORT_SYMBOL(mapconv_pp0_sel);
 void pp_output_cfg(struct starfive_crtc *sf_crtc, int ppNum, int outSel, int progInter, int desformat, int ptMode)
 {
 	int cfg = outSel | progInter << PP_INTERLACE
-			  | desformat << PP_DES_FORMAT
-			  | ptMode << PP_POINTER_MODE;
-
+			| desformat << PP_DES_FORMAT
+			| ptMode << PP_POINTER_MODE;
 	int preCfg = 0xfffff8f0 & sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL1);
+
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL1, cfg | preCfg);
 	PP_PRT("PP%d outSel: %d, outFormat: 0x%x, Out Interlace: %d, ptMode: %d\n",
 		ppNum, outSel, desformat, progInter, ptMode);
@@ -125,20 +131,21 @@ void pp_srcfmt_cfg(struct starfive_crtc *sf_crtc, int ppNum, int srcformat, int
 		int yuv420_mode, int argbOrd)
 {
 	int cfg = srcformat << PP_SRC_FORMAT_N | yuv420Inter << PP_420_ITLC
-						| yuv422_mode << PP_SRC_422_YUV_POS
-						| yuv420_mode << PP_SRC_420_YUV_POS
-						| argbOrd << PP_SRC_ARGB_ORDER;
-
+					| yuv422_mode << PP_SRC_422_YUV_POS
+					| yuv420_mode << PP_SRC_420_YUV_POS
+					| argbOrd << PP_SRC_ARGB_ORDER;
 	int preCfg = 0x83ffff0f & sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL1);
+
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL1, cfg | preCfg);
 	PP_PRT("PP%d Src Format: 0x%x, YUV420 Interlace: %d, YUV422: %d, YUV420: %d, ARGB Order: %d\n",
-		ppNum, srcformat,yuv420Inter,yuv422_mode,yuv420_mode, argbOrd);
+		ppNum, srcformat, yuv420Inter, yuv422_mode, yuv420_mode, argbOrd);
 }
 
 void pp_r2yscal_bypass(struct starfive_crtc *sf_crtc, int ppNum, int r2yByp, int scalByp, int y2rByp)
 {
 	int bypass = (r2yByp | scalByp<<1 | y2rByp<<2) << PP_R2Y_BPS;
 	int preCfg = 0xffff8fff & sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL1);
+
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL1, bypass | preCfg);
 	PP_PRT("PP%d Bypass R2Y: %d, Y2R: %d, MainSacle: %d\n", ppNum, r2yByp, y2rByp, scalByp);
 }
@@ -146,6 +153,7 @@ void pp_r2yscal_bypass(struct starfive_crtc *sf_crtc, int ppNum, int r2yByp, int
 void pp_argb_alpha(struct starfive_crtc *sf_crtc, int ppNum, int alpha)
 {
 	int preCfg = 0xff00ffff & sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL1);
+
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL1, alpha << PP_ARGB_ALPHA | preCfg);
 	PP_PRT("PP%d Alpha: 0x%4x\n", ppNum, alpha);
 }
@@ -154,9 +162,10 @@ void pp_argb_alpha(struct starfive_crtc *sf_crtc, int ppNum, int alpha)
 void pp_r2y_coeff(struct starfive_crtc *sf_crtc, int ppNum, int coefNum, int rcoef, int gcoef, int bcoef, int off)
 {
 	int rgcoeff = rcoef | gcoef << PP_COEF_G1;
-	int bcoefoff = bcoef| off << PP_OFFSET_1;
+	int bcoefoff = bcoef | off << PP_OFFSET_1;
 	u32 addr1 = (coefNum - 1) * 0x8 + PP_R2Y_COEF1;
 	u32 addr2 = (coefNum - 1) * 0x8 + PP_R2Y_COEF2;
+
 	sf_fb_vppwrite32(sf_crtc, ppNum, addr1, rgcoeff);
 	sf_fb_vppwrite32(sf_crtc, ppNum, addr2, bcoefoff);
 	PP_PRT("PP%d coefNum: %d, rCoef: 0x%4x, gCoef: 0x%4x, bCoef: 0x%4x, off: 0x%4x\n",
@@ -166,6 +175,7 @@ void pp_r2y_coeff(struct starfive_crtc *sf_crtc, int ppNum, int coefNum, int rco
 void pp_output_fmt_cfg(struct starfive_crtc *sf_crtc, int ppNum, int yuv420Inter, int yuv422_mode)
 {
 	int preCfg = 0xfffffffe & sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL2);
+
 	preCfg = preCfg | yuv420Inter << PP_DES_420_ORDER
 			| yuv422_mode << PP_DES_422_ORDER;
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL2, preCfg);
@@ -175,6 +185,7 @@ void pp_output_fmt_cfg(struct starfive_crtc *sf_crtc, int ppNum, int yuv420Inter
 void pp_lockTrans_cfg(struct starfive_crtc *sf_crtc, int ppNum, int lockTrans)
 {
 	int preCfg = 0xfffffffe & sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL2);
+
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL2, lockTrans | preCfg);
 	PP_PRT("PP%d Lock Transfer: %d\n", ppNum, lockTrans);
 }
@@ -182,21 +193,24 @@ void pp_lockTrans_cfg(struct starfive_crtc *sf_crtc, int ppNum, int lockTrans)
 void pp_int_interval_cfg(struct starfive_crtc *sf_crtc, int ppNum, int interval)
 {
 	int preCfg = 0xffff00ff & sf_fb_vppread32(sf_crtc, ppNum, PP_CTRL2);
+
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_CTRL2, interval << PP_INT_INTERVAL | preCfg);
 	PP_PRT("PP%d Frame Interrupt interval: %d Frames\n", ppNum, interval);
 }
 
 void pp_srcSize_cfg(struct starfive_crtc *sf_crtc, int ppNum, int hsize, int vsize)
 {
-  int size = hsize | vsize << PP_SRC_VSIZE;
-  sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_SIZE, size);
-  PP_PRT("PP%d HSize: %d, VSize: %d\n", ppNum, hsize, vsize);
+	int size = hsize | vsize << PP_SRC_VSIZE;
+
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_SIZE, size);
+	PP_PRT("PP%d HSize: %d, VSize: %d\n", ppNum, hsize, vsize);
 }
 
 //0-no drop, 1-1/2, 2-1/4, down to 1/32
 void pp_drop_cfg(struct starfive_crtc *sf_crtc, int ppNum, int hdrop, int vdrop)
 {
 	int drop = hdrop | vdrop << PP_DROP_VRATION;
+
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_DROP_CTRL, drop);
 	PP_PRT("PP%d HDrop: %d, VDrop: %d\n", ppNum, hdrop, vdrop);
 }
@@ -205,68 +219,69 @@ void pp_drop_cfg(struct starfive_crtc *sf_crtc, int ppNum, int hdrop, int vdrop)
 void pp_desSize_cfg(struct starfive_crtc *sf_crtc, int ppNum, int hsize, int vsize)
 {
 	int size = hsize | vsize << PP_DES_VSIZE;
+
 	sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_SIZE, size);
 	PP_PRT("PP%d HSize: %d, VSize: %d\n", ppNum, hsize, vsize);
 }
 
 void pp_desAddr_cfg(struct starfive_crtc *sf_crtc, int ppNum, int yaddr, int uaddr, int vaddr)
 {
-   sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_Y_SA, yaddr);
-   sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_U_SA, uaddr);
-   sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_V_SA, vaddr);
-   PP_PRT("PP%d des-Addr Y: 0x%8x, U: 0x%8x, V: 0x%8x\n", ppNum, yaddr, uaddr, vaddr);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_Y_SA, yaddr);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_U_SA, uaddr);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_V_SA, vaddr);
+	PP_PRT("PP%d des-Addr Y: 0x%8x, U: 0x%8x, V: 0x%8x\n", ppNum, yaddr, uaddr, vaddr);
 }
 
 void pp_desOffset_cfg(struct starfive_crtc *sf_crtc, int ppNum, int yoff, int uoff, int voff)
 {
-   sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_Y_OFS, yoff);
-   sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_U_OFS, uoff);
-   sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_V_OFS, voff);
-   PP_PRT("PP%d des-Offset Y: 0x%4x, U: 0x%4x, V: 0x%4x\n", ppNum, yoff, uoff, voff);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_Y_OFS, yoff);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_U_OFS, uoff);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_DES_V_OFS, voff);
+	PP_PRT("PP%d des-Offset Y: 0x%4x, U: 0x%4x, V: 0x%4x\n", ppNum, yoff, uoff, voff);
 }
 
 
 void pp_intcfg(struct starfive_crtc *sf_crtc, int ppNum, int intMask)
 {
-   int intcfg = ~(0x1<<0);
+	int intcfg = ~(0x1<<0);
 
-   if(intMask)
-       intcfg = 0xf;
-   sf_fb_vppwrite32(sf_crtc, ppNum, PP_INT_MASK, intcfg);
+	if (intMask)
+		intcfg = 0xf;
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_INT_MASK, intcfg);
 }
 EXPORT_SYMBOL(pp_intcfg);
 
 //next source frame Y/RGB start address, ?
 void pp_srcAddr_next(struct starfive_crtc *sf_crtc, int ppNum, int ysa, int usa, int vsa)
 {
-  sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_Y_SA_NXT, ysa);
-  sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_U_SA_NXT, usa);
-  sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_V_SA_NXT, vsa);
-  PP_PRT("PP%d next Y startAddr: 0x%8x, U startAddr: 0x%8x, V startAddr: 0x%8x\n", ppNum, ysa, usa, vsa);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_Y_SA_NXT, ysa);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_U_SA_NXT, usa);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_V_SA_NXT, vsa);
+	PP_PRT("PP%d next Y startAddr: 0x%8x, U startAddr: 0x%8x, V startAddr: 0x%8x\n", ppNum, ysa, usa, vsa);
 }
 EXPORT_SYMBOL(pp_srcAddr_next);
 
 void pp_srcOffset_cfg(struct starfive_crtc *sf_crtc, int ppNum, int yoff, int uoff, int voff)
 {
-   sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_Y_OFS, yoff);
-   sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_U_OFS, uoff);
-   sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_V_OFS, voff);
-   PP_PRT("PP%d src-Offset Y: 0x%4x, U: 0x%4x, V: 0x%4x\n", ppNum, yoff, uoff, voff);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_Y_OFS, yoff);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_U_OFS, uoff);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_SRC_V_OFS, voff);
+	PP_PRT("PP%d src-Offset Y: 0x%4x, U: 0x%4x, V: 0x%4x\n", ppNum, yoff, uoff, voff);
 }
 EXPORT_SYMBOL(pp_srcOffset_cfg);
 
 void pp_nxtAddr_load(struct starfive_crtc *sf_crtc, int ppNum, int nxtPar, int nxtPos)
 {
-  sf_fb_vppwrite32(sf_crtc, ppNum, PP_LOAD_NXT_PAR, nxtPar | nxtPos);
-  PP_PRT("PP%d next addrPointer: %d, %d set Regs\n", ppNum, nxtPar, nxtPos);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_LOAD_NXT_PAR, nxtPar | nxtPos);
+	PP_PRT("PP%d next addrPointer: %d, %d set Regs\n", ppNum, nxtPar, nxtPos);
 }
 EXPORT_SYMBOL(pp_nxtAddr_load);
 
 void pp_run(struct starfive_crtc *sf_crtc, int ppNum, int start)
 {
-   sf_fb_vppwrite32(sf_crtc, ppNum, PP_SWITCH, start);
-   //if(start)
-   //  PP_PRT("Now start the PP%d\n\n", ppNum);
+	sf_fb_vppwrite32(sf_crtc, ppNum, PP_SWITCH, start);
+	//if(start)
+	//  PP_PRT("Now start the PP%d\n\n", ppNum);
 }
 EXPORT_SYMBOL(pp_run);
 
@@ -293,328 +308,319 @@ EXPORT_SYMBOL(pp_disable_intr);
 
 static void pp_srcfmt_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mode *src)
 {
-    switch(src->format)
-    {
-        case COLOR_YUV422_YVYU:
-			PP_INFO("src_format: COLOR_YUV422_YVYU\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_YVYU, 0x0, 0x0);
-            break;
-        case COLOR_YUV422_VYUY:
-			PP_INFO("src_format: COLOR_YUV422_VYUY\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_VYUY, 0x0, 0x0);
-            break;
-        case COLOR_YUV422_YUYV:
-			PP_INFO("src_format: COLOR_YUV422_YUYV\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_YUYV, 0x0, 0x0);
-            break;
-        case COLOR_YUV422_UYVY:
-			PP_INFO("src_format: COLOR_YUV422_UYVY\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_UYVY, 0x0, 0x0);
-            break;
-        case COLOR_YUV420P:
-			PP_INFO("src_format: COLOR_YUV420P\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420P, 0x0, 0, 0x0, 0x0);
-            break;
-        case COLOR_YUV420_NV12:
-			PP_INFO("src_format: COLOR_YUV420_NV21\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420I, 0x1, 0, COLOR_YUV420_NV12-COLOR_YUV420_NV12, 0x0);
-            break;
-        case COLOR_YUV420_NV21:
-			PP_INFO("src_format: COLOR_YUV420_NV12\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420I, 0x1, 0, COLOR_YUV420_NV21-COLOR_YUV420_NV12, 0x0);
-            break;
-        case COLOR_RGB888_ARGB:
-			PP_INFO("src_format: COLOR_RGB888_ARGB\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_ARGB-COLOR_RGB888_ARGB);//0x0);
-            break;
-        case COLOR_RGB888_ABGR:
-			PP_INFO("src_format: COLOR_RGB888_ABGR\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_ABGR-COLOR_RGB888_ARGB);//0x1);
-            break;
-        case COLOR_RGB888_RGBA:
-			PP_INFO("src_format: COLOR_RGB888_RGBA\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_RGBA-COLOR_RGB888_ARGB);//0x2);
-            break;
-        case COLOR_RGB888_BGRA:
-			PP_INFO("src_format: COLOR_RGB888_BGRA\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_BGRA-COLOR_RGB888_ARGB);//0x3);
-            break;
-        case COLOR_RGB565:
-			PP_INFO("src_format: COLOR_RGB888_RGB565\n");
-            pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_RGB565, 0x0, 0x0, 0x0, 0x0);
-            break;
-    }
+	switch (src->format) {
+	case COLOR_YUV422_YVYU:
+		PP_INFO("src_format: COLOR_YUV422_YVYU\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_YVYU, 0x0, 0x0);
+		break;
+	case COLOR_YUV422_VYUY:
+		PP_INFO("src_format: COLOR_YUV422_VYUY\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_VYUY, 0x0, 0x0);
+		break;
+	case COLOR_YUV422_YUYV:
+		PP_INFO("src_format: COLOR_YUV422_YUYV\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_YUYV, 0x0, 0x0);
+		break;
+	case COLOR_YUV422_UYVY:
+		PP_INFO("src_format: COLOR_YUV422_UYVY\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV422, 0x0, COLOR_YUV422_UYVY, 0x0, 0x0);
+		break;
+	case COLOR_YUV420P:
+		PP_INFO("src_format: COLOR_YUV420P\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420P, 0x0, 0, 0x0, 0x0);
+		break;
+	case COLOR_YUV420_NV12:
+		PP_INFO("src_format: COLOR_YUV420_NV21\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420I, 0x1, 0, COLOR_YUV420_NV12-COLOR_YUV420_NV12, 0x0);
+		break;
+	case COLOR_YUV420_NV21:
+		PP_INFO("src_format: COLOR_YUV420_NV12\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_YUV420I, 0x1, 0, COLOR_YUV420_NV21-COLOR_YUV420_NV12, 0x0);
+		break;
+	case COLOR_RGB888_ARGB:
+		PP_INFO("src_format: COLOR_RGB888_ARGB\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_ARGB-COLOR_RGB888_ARGB);//0x0);
+		break;
+	case COLOR_RGB888_ABGR:
+		PP_INFO("src_format: COLOR_RGB888_ABGR\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_ABGR-COLOR_RGB888_ARGB);//0x1);
+		break;
+	case COLOR_RGB888_RGBA:
+		PP_INFO("src_format: COLOR_RGB888_RGBA\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_RGBA-COLOR_RGB888_ARGB);//0x2);
+		break;
+	case COLOR_RGB888_BGRA:
+		PP_INFO("src_format: COLOR_RGB888_BGRA\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_GRB888, 0x0, 0x0, 0x0, COLOR_RGB888_BGRA-COLOR_RGB888_ARGB);//0x3);
+		break;
+	case COLOR_RGB565:
+		PP_INFO("src_format: COLOR_RGB888_RGB565\n");
+		pp_srcfmt_cfg(sf_crtc, ppNum, PP_SRC_RGB565, 0x0, 0x0, 0x0, 0x0);
+		break;
+	}
 }
 
 static void pp_dstfmt_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mode *dst)
 {
-    unsigned int outsel = 1;
-    if(dst->addr)
-    {
-        outsel = 0;
-    }
-
-    switch(dst->format) {
-        case COLOR_YUV422_YVYU:
-			PP_INFO("dst_format: COLOR_YUV422_YVYU\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
-            pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YVYU);
-            break;
-        case COLOR_YUV422_VYUY:
-			PP_INFO("dst_format: COLOR_YUV422_VYUY\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
-            pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_VYUY);
-            break;
-        case COLOR_YUV422_YUYV:
-			PP_INFO("dst_format: COLOR_YUV422_YUYV\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
-            pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YUYV);
-            break;
-        case COLOR_YUV422_UYVY:
-			PP_INFO("dst_format: COLOR_YUV422_UYVY\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
-            pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YVYU);
-            break;
-        case COLOR_YUV420P:
-			PP_INFO("dst_format: COLOR_YUV420P\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420P, 0x0);
-            pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
-            break;
-        case COLOR_YUV420_NV12:
-			PP_INFO("dst_format: COLOR_YUV420_NV21\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420I, 0x0);
-            pp_output_fmt_cfg(sf_crtc, ppNum, COLOR_YUV420_NV12 - COLOR_YUV420_NV12, 0);
-            break;
-        case COLOR_YUV420_NV21:
-			PP_INFO("dst_format: COLOR_YUV420_NV12\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420I, 0x0);///0x2, 0x0);
-            pp_output_fmt_cfg(sf_crtc, ppNum, COLOR_YUV420_NV21 - COLOR_YUV420_NV12, 0);
-            break;
-        case COLOR_RGB888_ARGB:
-			PP_INFO("dst_format: COLOR_RGB888_ARGB\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_ARGB888, 0x0);
-            //pp_output_fmt_cfg(ppNum, 0, 0);
-            break;
-        case COLOR_RGB888_ABGR:
-			PP_INFO("dst_format: COLOR_RGB888_ABGR\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_ABGR888, 0x0);
-            pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
-            break;
-        case COLOR_RGB888_RGBA:
-			PP_INFO("dst_format: COLOR_RGB888_RGBA\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_RGBA888, 0x0);
-            pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
-            break;
-        case COLOR_RGB888_BGRA:
-			PP_INFO("dst_format: COLOR_RGB888_BGRA\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_BGRA888, 0x0);
-            pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
-            break;
-        case COLOR_RGB565:
-			PP_INFO("dst_format: COLOR_RGB565\n");
-            pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_RGB565, 0x0);
-            pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
-            break;
-    }
+	unsigned int outsel = 1;
+
+	if (dst->addr)
+		outsel = 0;
+
+	switch (dst->format) {
+	case COLOR_YUV422_YVYU:
+		PP_INFO("dst_format: COLOR_YUV422_YVYU\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
+		pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YVYU);
+		break;
+	case COLOR_YUV422_VYUY:
+		PP_INFO("dst_format: COLOR_YUV422_VYUY\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
+		pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_VYUY);
+		break;
+	case COLOR_YUV422_YUYV:
+		PP_INFO("dst_format: COLOR_YUV422_YUYV\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
+		pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YUYV);
+		break;
+	case COLOR_YUV422_UYVY:
+		PP_INFO("dst_format: COLOR_YUV422_UYVY\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV422, 0x0);
+		pp_output_fmt_cfg(sf_crtc, ppNum, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YVYU);
+		break;
+	case COLOR_YUV420P:
+		PP_INFO("dst_format: COLOR_YUV420P\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420P, 0x0);
+		pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
+		break;
+	case COLOR_YUV420_NV12:
+		PP_INFO("dst_format: COLOR_YUV420_NV21\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420I, 0x0);
+		pp_output_fmt_cfg(sf_crtc, ppNum, COLOR_YUV420_NV12 - COLOR_YUV420_NV12, 0);
+		break;
+	case COLOR_YUV420_NV21:
+		PP_INFO("dst_format: COLOR_YUV420_NV12\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_YUV420I, 0x0);///0x2, 0x0);
+		pp_output_fmt_cfg(sf_crtc, ppNum, COLOR_YUV420_NV21 - COLOR_YUV420_NV12, 0);
+		break;
+	case COLOR_RGB888_ARGB:
+		PP_INFO("dst_format: COLOR_RGB888_ARGB\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_ARGB888, 0x0);
+		//pp_output_fmt_cfg(ppNum, 0, 0);
+		break;
+	case COLOR_RGB888_ABGR:
+		PP_INFO("dst_format: COLOR_RGB888_ABGR\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_ABGR888, 0x0);
+		pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
+		break;
+	case COLOR_RGB888_RGBA:
+		PP_INFO("dst_format: COLOR_RGB888_RGBA\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_RGBA888, 0x0);
+		pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
+		break;
+	case COLOR_RGB888_BGRA:
+		PP_INFO("dst_format: COLOR_RGB888_BGRA\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_BGRA888, 0x0);
+		pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
+		break;
+	case COLOR_RGB565:
+		PP_INFO("dst_format: COLOR_RGB565\n");
+		pp_output_cfg(sf_crtc, ppNum, outsel, 0x0, PP_DST_RGB565, 0x0);
+		pp_output_fmt_cfg(sf_crtc, ppNum, 0, 0);
+		break;
+	}
 }
 
 
 void pp_format_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mode *src, struct pp_video_mode *dst)
 {
+	/* 1:bypass, 0:not bypass */
+	unsigned int scale_byp = 1;
+
+	pp_srcfmt_set(sf_crtc, ppNum, src);
+	pp_dstfmt_set(sf_crtc, ppNum, dst);
+
+	if ((src->height != dst->height) || (src->width != dst->width))
+		scale_byp = 0;
+
+	if ((src->format >= COLOR_RGB888_ARGB) && (dst->format <= COLOR_YUV420_NV12)) {
+		/* rgb -> yuv-420 */
+		pp_r2yscal_bypass(sf_crtc, ppNum, NOT_BYPASS, scale_byp, BYPASS);
+		pp_r2y_coeff(sf_crtc, ppNum, 1, R2Y_COEF_R1, R2Y_COEF_G1, R2Y_COEF_B1, R2Y_OFFSET1);
+		pp_r2y_coeff(sf_crtc, ppNum, 2, R2Y_COEF_R2, R2Y_COEF_G2, R2Y_COEF_B2, R2Y_OFFSET2);
+		pp_r2y_coeff(sf_crtc, ppNum, 3, R2Y_COEF_R3, R2Y_COEF_G3, R2Y_COEF_B3, R2Y_OFFSET3);
+	} else if ((src->format <= COLOR_YUV420_NV12) && (dst->format >= COLOR_RGB888_ARGB)) {
+		/* yuv-420 -> rgb */
+		pp_r2yscal_bypass(sf_crtc, ppNum, BYPASS, scale_byp, NOT_BYPASS);
+	} else if ((src->format <= COLOR_YUV422_YVYU) && (dst->format <= COLOR_YUV420_NV12)) {
+		/* yuv422 -> yuv420 */
+		pp_r2yscal_bypass(sf_crtc, ppNum, BYPASS, scale_byp, BYPASS);
+	} else {
+		/* rgb565->argb888 */
+		pp_r2yscal_bypass(sf_crtc, ppNum, BYPASS, scale_byp, BYPASS);
+	} //else if((src->format >= COLOR_RGB888_ARGB) && (dst->format >= COLOR_RGB888_ARGB))
+
+	pp_argb_alpha(sf_crtc, ppNum, 0xff);
 
-    /* 1:bypass, 0:not bypass */
-    unsigned int scale_byp = 1;
-
-    pp_srcfmt_set(sf_crtc, ppNum, src);
-    pp_dstfmt_set(sf_crtc, ppNum, dst);
-
-    if((src->height != dst->height) || (src->width != dst->width)) {
-        scale_byp = 0;
-    }
-
-    if((src->format >= COLOR_RGB888_ARGB) && (dst->format <= COLOR_YUV420_NV12)) {
-        /* rgb -> yuv-420 */
-        pp_r2yscal_bypass(sf_crtc, ppNum, NOT_BYPASS, scale_byp, BYPASS);
-        pp_r2y_coeff(sf_crtc, ppNum, 1, R2Y_COEF_R1, R2Y_COEF_G1, R2Y_COEF_B1, R2Y_OFFSET1);
-        pp_r2y_coeff(sf_crtc, ppNum, 2, R2Y_COEF_R2, R2Y_COEF_G2, R2Y_COEF_B2, R2Y_OFFSET2);
-        pp_r2y_coeff(sf_crtc, ppNum, 3, R2Y_COEF_R3, R2Y_COEF_G3, R2Y_COEF_B3, R2Y_OFFSET3);
-    } else if ((src->format <= COLOR_YUV420_NV12) && (dst->format >= COLOR_RGB888_ARGB)) {
-        /* yuv-420 -> rgb */
-        pp_r2yscal_bypass(sf_crtc, ppNum, BYPASS, scale_byp, NOT_BYPASS);
-    } else if ((src->format <= COLOR_YUV422_YVYU) && (dst->format <= COLOR_YUV420_NV12)) {
-        /* yuv422 -> yuv420 */
-        pp_r2yscal_bypass(sf_crtc, ppNum, BYPASS, scale_byp, BYPASS);
-    } else {
-        /* rgb565->argb888 */
-        pp_r2yscal_bypass(sf_crtc, ppNum, BYPASS, scale_byp, BYPASS);
-    } //else if((src->format >= COLOR_RGB888_ARGB) && (dst->format >= COLOR_RGB888_ARGB))
-    {
-        /* rgb -> rgb */
-       // pp_r2yscal_bypass(ppNum, BYPASS, scale_byp, BYPASS);
-    }
-    pp_argb_alpha(sf_crtc, ppNum, 0xff);
-
-    if(dst->addr) {
-        pp_lockTrans_cfg(sf_crtc, ppNum, SYS_BUS_OUTPUT);
-    } else {
-        pp_lockTrans_cfg(sf_crtc, ppNum, FIFO_OUTPUT);
-    }
-
-    pp_int_interval_cfg(sf_crtc, ppNum, 0x1);
+	if (dst->addr)
+		pp_lockTrans_cfg(sf_crtc, ppNum, SYS_BUS_OUTPUT);
+	else
+		pp_lockTrans_cfg(sf_crtc, ppNum, FIFO_OUTPUT);
 
+	pp_int_interval_cfg(sf_crtc, ppNum, 0x1);
 }
 
 void pp_size_set(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_mode *src, struct pp_video_mode *dst)
 {
-    uint32_t srcAddr, dstaddr;
-    unsigned int size, y_rgb_ofst, uofst;
+	uint32_t srcAddr, dstaddr;
+	unsigned int size, y_rgb_ofst, uofst;
 	unsigned int v_uvofst = 0, next_y_rgb_addr = 0, next_u_addr = 0, next_v_addr = 0;
-    unsigned int i = 0;
-
-    pp_srcSize_cfg(sf_crtc, ppNum, src->width - 1, src->height - 1);
-    pp_drop_cfg(sf_crtc, ppNum, 0x0, 0x0);///0:no drop
-    pp_desSize_cfg(sf_crtc, ppNum, dst->width - 1, dst->height - 1);
-
-    srcAddr = src->addr + (i<<30);///PP_SRC_BASE_ADDR + (i<<30);
-    size = src->width * src->height;
-
-    if(src->format >= COLOR_RGB888_ARGB) {
-        next_y_rgb_addr = srcAddr;
-        next_u_addr = 0;
-        next_v_addr = 0;
-
-        y_rgb_ofst = 0;
-        uofst = 0;
-        v_uvofst = 0;
-
-        //pp_srcAddr_next(ppNum, srcAddr, 0, 0);
-        //pp_srcOffset_cfg(ppNum, 0x0, 0x0, 0x0);
-
-    } else {
-        //if((src->format == COLOR_YUV420_NV21) || (src->format == COLOR_YUV420_NV12)){
-        if(src->format == COLOR_YUV420_NV21) {    //ok
-            next_y_rgb_addr = srcAddr;
-            next_u_addr = srcAddr+size+1;
-            next_v_addr = srcAddr+size;
-            y_rgb_ofst = 0;
-            uofst = 0;
-            v_uvofst = size;
-        } else if (src->format == COLOR_YUV420_NV12) {
-            next_y_rgb_addr = srcAddr;
-            next_u_addr = srcAddr+size;
-            next_v_addr = srcAddr+size+1;
-            y_rgb_ofst = 0;
-            uofst = 0;
-            v_uvofst = size;
-        } else if (src->format == COLOR_YUV420P) {
-            next_y_rgb_addr = srcAddr;
-            next_u_addr = srcAddr+size;
-            next_v_addr = srcAddr+size*5/4;
-            y_rgb_ofst = 0;
-            uofst = 0;
-            v_uvofst = 0;
-        } else if (src->format == COLOR_YUV422_YVYU) {   //ok
-            next_y_rgb_addr = srcAddr;
-            next_u_addr = srcAddr+1;
-            next_v_addr = srcAddr+3;
-            y_rgb_ofst = 0;
-            uofst = 0;
-            v_uvofst = 0;
-        } else if (src->format == COLOR_YUV422_VYUY) {   //ok
-            next_y_rgb_addr = srcAddr+1;
-            next_u_addr = srcAddr+2;
-            next_v_addr = srcAddr;
-            y_rgb_ofst = 0;
-            uofst = 0;
-            v_uvofst = 0;
-        } else if(src->format == COLOR_YUV422_YUYV) {   //ok
-            next_y_rgb_addr = srcAddr;
-            next_u_addr = srcAddr+1;
-            next_v_addr = srcAddr+2;
-            y_rgb_ofst = 0;
-            uofst = 0;
-            v_uvofst = 0;
-        } else if(src->format == COLOR_YUV422_UYVY) {  //ok
-            next_y_rgb_addr = srcAddr+1;
-            next_u_addr = srcAddr;
-            next_v_addr = srcAddr+2;
-            y_rgb_ofst = 0;
-            uofst = 0;
-            v_uvofst = 0;
-        }
-    }
-    pp_srcAddr_next(sf_crtc, ppNum, next_y_rgb_addr, next_u_addr, next_v_addr);
-    pp_srcOffset_cfg(sf_crtc, ppNum, y_rgb_ofst, uofst, v_uvofst);
-    /* source addr not change */
-    pp_nxtAddr_load(sf_crtc, ppNum, 0x1, (i & 0x1));
-
-    if(dst->addr) {
-        dstaddr = dst->addr;
-        size = dst->height*dst->width;
-        if(dst->format >= COLOR_RGB888_ARGB) {
-            next_y_rgb_addr = dstaddr;
-            next_u_addr = 0;
-            next_v_addr = 0;
-            y_rgb_ofst = 0;
-            uofst = 0;
-            v_uvofst = 0;
-        } else {
-            if(dst->format == COLOR_YUV420_NV21) {
+	unsigned int i = 0;
+
+	pp_srcSize_cfg(sf_crtc, ppNum, src->width - 1, src->height - 1);
+	pp_drop_cfg(sf_crtc, ppNum, 0x0, 0x0);///0:no drop
+	pp_desSize_cfg(sf_crtc, ppNum, dst->width - 1, dst->height - 1);
+
+	srcAddr = src->addr + (i<<30);///PP_SRC_BASE_ADDR + (i<<30);
+	size = src->width * src->height;
+
+	if (src->format >= COLOR_RGB888_ARGB) {
+		next_y_rgb_addr = srcAddr;
+		next_u_addr = 0;
+		next_v_addr = 0;
+
+		y_rgb_ofst = 0;
+		uofst = 0;
+		v_uvofst = 0;
+
+		//pp_srcAddr_next(ppNum, srcAddr, 0, 0);
+		//pp_srcOffset_cfg(ppNum, 0x0, 0x0, 0x0);
+
+	} else {
+		//if((src->format == COLOR_YUV420_NV21) || (src->format == COLOR_YUV420_NV12)){
+		if (src->format == COLOR_YUV420_NV21) {    //ok
+			next_y_rgb_addr = srcAddr;
+			next_u_addr = srcAddr + size + 1;
+			next_v_addr = srcAddr + size;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = size;
+		} else if (src->format == COLOR_YUV420_NV12) {
+			next_y_rgb_addr = srcAddr;
+			next_u_addr = srcAddr + size;
+			next_v_addr = srcAddr + size + 1;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = size;
+		} else if (src->format == COLOR_YUV420P) {
+			next_y_rgb_addr = srcAddr;
+			next_u_addr = srcAddr + size;
+			next_v_addr = srcAddr + size * 5 / 4;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		} else if (src->format == COLOR_YUV422_YVYU) {   //ok
+			next_y_rgb_addr = srcAddr;
+			next_u_addr = srcAddr + 1;
+			next_v_addr = srcAddr + 3;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		} else if (src->format == COLOR_YUV422_VYUY) {   //ok
+			next_y_rgb_addr = srcAddr + 1;
+			next_u_addr = srcAddr + 2;
+			next_v_addr = srcAddr;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		} else if (src->format == COLOR_YUV422_YUYV) {   //ok
+			next_y_rgb_addr = srcAddr;
+			next_u_addr = srcAddr + 1;
+			next_v_addr = srcAddr + 2;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		} else if (src->format == COLOR_YUV422_UYVY) {  //ok
+			next_y_rgb_addr = srcAddr + 1;
+			next_u_addr = srcAddr;
+			next_v_addr = srcAddr + 2;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		}
+	}
+	pp_srcAddr_next(sf_crtc, ppNum, next_y_rgb_addr, next_u_addr, next_v_addr);
+	pp_srcOffset_cfg(sf_crtc, ppNum, y_rgb_ofst, uofst, v_uvofst);
+	/* source addr not change */
+	pp_nxtAddr_load(sf_crtc, ppNum, 0x1, (i & 0x1));
+
+	if (dst->addr) {
+		dstaddr = dst->addr;
+		size = dst->height * dst->width;
+		if (dst->format >= COLOR_RGB888_ARGB) {
+			next_y_rgb_addr = dstaddr;
+			next_u_addr = 0;
+			next_v_addr = 0;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		} else {
+			if (dst->format == COLOR_YUV420_NV21) {
 				/* yyyyvuvuvu */
-                next_y_rgb_addr = dstaddr;
-                next_u_addr = dstaddr+size;
-                next_v_addr = 0;//dstaddr+size;
-                y_rgb_ofst = 0;
-                uofst = 0;
-                v_uvofst = 0;
-            } else if (dst->format == COLOR_YUV420_NV12){
+				next_y_rgb_addr = dstaddr;
+				next_u_addr = dstaddr + size;
+				next_v_addr = 0;//dstaddr+size;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV420_NV12) {
 				/* yyyyuvuvuv */
-                next_y_rgb_addr = dstaddr;
-                next_u_addr = dstaddr+size;
-                next_v_addr = dstaddr+size+1;
-                y_rgb_ofst = 0;
-                uofst = size;
-                v_uvofst = 0;
-            } else if(dst->format == COLOR_YUV420P) {
-                next_y_rgb_addr = dstaddr;
-                next_u_addr = dstaddr+size;
-                next_v_addr = dstaddr+size*5/4;
-                y_rgb_ofst = 0;
-                uofst = 0;
-                v_uvofst = 0;
-            } else if (dst->format == COLOR_YUV422_YVYU) {
-                next_y_rgb_addr = dstaddr;
-                next_u_addr = dstaddr+1;
-                next_v_addr = dstaddr+3;
-                y_rgb_ofst = 0;
-                uofst = 0;
-                v_uvofst = 0;
-            } else if(dst->format == COLOR_YUV422_VYUY) {
-                next_y_rgb_addr = dstaddr+1;
-                next_u_addr = dstaddr+2;
-                next_v_addr = dstaddr;
-                y_rgb_ofst = 0;
-                uofst = 0;
-                v_uvofst = 0;
-            } else if(dst->format == COLOR_YUV422_YUYV) {
-                next_y_rgb_addr = dstaddr;
-                next_u_addr = dstaddr+1;
-                next_v_addr = dstaddr+2;
-                y_rgb_ofst = 0;
-                uofst = 0;
-                v_uvofst = 0;
-            } else if(dst->format == COLOR_YUV422_UYVY) {
-                next_y_rgb_addr = dstaddr+1;
-                next_u_addr = dstaddr;
-                next_v_addr = dstaddr+2;
-                y_rgb_ofst = 0;
-                uofst = 0;
-                v_uvofst = 0;
-            }
-        }
-        pp_desAddr_cfg(sf_crtc, ppNum, next_y_rgb_addr, next_u_addr, next_v_addr);
-        pp_desOffset_cfg(sf_crtc, ppNum, y_rgb_ofst, uofst, v_uvofst);
-    }
+				next_y_rgb_addr = dstaddr;
+				next_u_addr = dstaddr + size;
+				next_v_addr = dstaddr + size + 1;
+				y_rgb_ofst = 0;
+				uofst = size;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV420P) {
+				next_y_rgb_addr = dstaddr;
+				next_u_addr = dstaddr + size;
+				next_v_addr = dstaddr + size * 5 / 4;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV422_YVYU) {
+				next_y_rgb_addr = dstaddr;
+				next_u_addr = dstaddr + 1;
+				next_v_addr = dstaddr + 3;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV422_VYUY) {
+				next_y_rgb_addr = dstaddr + 1;
+				next_u_addr = dstaddr + 2;
+				next_v_addr = dstaddr;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV422_YUYV) {
+				next_y_rgb_addr = dstaddr;
+				next_u_addr = dstaddr + 1;
+				next_v_addr = dstaddr + 2;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV422_UYVY) {
+				next_y_rgb_addr = dstaddr + 1;
+				next_u_addr = dstaddr;
+				next_v_addr = dstaddr + 2;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			}
+		}
+		pp_desAddr_cfg(sf_crtc, ppNum, next_y_rgb_addr, next_u_addr, next_v_addr);
+		pp_desOffset_cfg(sf_crtc, ppNum, y_rgb_ofst, uofst, v_uvofst);
+	}
 
 }
 
@@ -629,46 +635,42 @@ static void pp_config(struct starfive_crtc *sf_crtc, int ppNum, struct pp_video_
 irqreturn_t vpp1_isr_handler(int this_irq, void *dev_id)
 {
 	struct starfive_crtc *sf_crtc = (struct starfive_crtc *)dev_id;
-	static int count = 0;
-
+	static int count;
 	u32 intr_status = 0;
 
-	intr_status = sf_fb_vppread32(sf_crtc, 1,PP_INT_STATUS);
+	intr_status = sf_fb_vppread32(sf_crtc, 1, PP_INT_STATUS);
 	sf_fb_vppwrite32(sf_crtc, 1, PP_INT_CLR, 0xf);
 
-
-	count ++;
-	//if(0 == count % 100)
-		//PP_PRT("pp count = %d, intr_status = 0x%x\n", count, intr_status);
+	count++;
 
 	return IRQ_HANDLED;
 }
 EXPORT_SYMBOL(vpp1_isr_handler);
 
 
-static void starfive_pp_enable_intr(struct starfive_crtc *sf_crtc, int enable) {
+static void starfive_pp_enable_intr(struct starfive_crtc *sf_crtc, int enable)
+{
 	int pp_id;
 
 	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
-		if(1 == sf_crtc->pp[pp_id].inited) {
-			if (enable) {
+		if (sf_crtc->pp[pp_id].inited == 1) {
+			if (enable)
 				pp_enable_intr(sf_crtc, pp_id);
-			} else {
+			else
 				pp_disable_intr(sf_crtc, pp_id);
-			}
 		}
 	}
 }
 
 static int starfive_pp_video_mode_init(struct starfive_crtc *sf_crtc, struct pp_video_mode *src,
-		struct pp_video_mode *dst, int pp_id) {
-
-	if ((NULL == src) || (NULL == dst)) {
+		struct pp_video_mode *dst, int pp_id)
+{
+	if ((!src) || (!dst)) {
 		dev_err(sf_crtc->dev, "Invalid argument!\n");
 		return -EINVAL;
 	}
 
-	if ((pp_id < PP_NUM) && (pp_id >= 0 )) {
+	if ((pp_id < PP_NUM) && (pp_id >= 0)) {
 		src->format = sf_crtc->vpp_format;
 		src->width = sf_crtc->crtc.state->adjusted_mode.hdisplay;
 		src->height = sf_crtc->crtc.state->adjusted_mode.vdisplay;
@@ -677,9 +679,9 @@ static int starfive_pp_video_mode_init(struct starfive_crtc *sf_crtc, struct pp_
 		dst->format = sf_crtc->pp[pp_id].dst.format;
 		dst->width = sf_crtc->crtc.state->adjusted_mode.hdisplay;
 		dst->height = sf_crtc->crtc.state->adjusted_mode.vdisplay;
-		if(true == sf_crtc->pp[pp_id].bus_out)	/*out to ddr*/
+		if (sf_crtc->pp[pp_id].bus_out)	/*out to ddr*/
 			dst->addr = 0xfc000000;
-		else if (true == sf_crtc->pp[pp_id].fifo_out)	/*out to lcdc*/
+		else if (sf_crtc->pp[pp_id].fifo_out)	/*out to lcdc*/
 			dst->addr = 0;
 	} else {
 		dev_err(sf_crtc->dev, "pp_id %d is not support\n", pp_id);
@@ -689,13 +691,14 @@ static int starfive_pp_video_mode_init(struct starfive_crtc *sf_crtc, struct pp_
 	return 0;
 }
 
-static int starfive_pp_init(struct starfive_crtc *sf_crtc) {
+static int starfive_pp_init(struct starfive_crtc *sf_crtc)
+{
 	int pp_id;
 	int ret = 0;
 	struct pp_video_mode src, dst;
 
 	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
-		if(1 == sf_crtc->pp[pp_id].inited) {
+		if (sf_crtc->pp[pp_id].inited == 1) {
 			ret = starfive_pp_video_mode_init(sf_crtc, &src, &dst, pp_id);
 			if (!ret)
 				pp_config(sf_crtc, pp_id, &src, &dst);
@@ -705,14 +708,14 @@ static int starfive_pp_init(struct starfive_crtc *sf_crtc) {
 	return ret;
 }
 
-static int starfive_pp_run(struct starfive_crtc *sf_crtc) {
+static int starfive_pp_run(struct starfive_crtc *sf_crtc)
+{
 	int pp_id;
 	int ret = 0;
 
 	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
-		if(1 == sf_crtc->pp[pp_id].inited) {
+		if (sf_crtc->pp[pp_id].inited == 1)
 			pp_run(sf_crtc, pp_id, PP_RUN);
-		}
 	}
 
 	return ret;
@@ -722,12 +725,10 @@ int starfive_pp_enable(struct starfive_crtc *sf_crtc)
 {
 	starfive_pp_enable_intr(sf_crtc, PP_INTR_DISABLE);
 
- 	if (starfive_pp_init(sf_crtc)) {
+	if (starfive_pp_init(sf_crtc))
 		return -ENODEV;
-	}
 
 	starfive_pp_run(sf_crtc);
-
 	starfive_pp_enable_intr(sf_crtc, PP_INTR_ENABLE);
 
 	return 0;
@@ -743,10 +744,9 @@ int starfive_pp_update(struct starfive_crtc *sf_crtc)
 	struct pp_video_mode src, dst;
 
 	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
-		if(1 == sf_crtc->pp[pp_id].inited) {
+		if (sf_crtc->pp[pp_id].inited == 1) {
 			ret = starfive_pp_video_mode_init(sf_crtc, &src, &dst, pp_id);
-			if (!ret)
-			{
+			if (!ret) {
 				pp_format_set(sf_crtc, pp_id, &src, &dst);
 				pp_size_set(sf_crtc, pp_id, &src, &dst);
 			}
@@ -764,11 +764,9 @@ int starfive_pp_get_2lcdc_id(struct starfive_crtc *sf_crtc)
 	int pp_id;
 
 	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
-		if(1 == sf_crtc->pp[pp_id].inited) {
-			if ((1 == sf_crtc->pp[pp_id].fifo_out)&& (0 == sf_crtc->pp[pp_id].bus_out))
-			{
+		if (sf_crtc->pp[pp_id].inited == 1) {
+			if ((sf_crtc->pp[pp_id].fifo_out == 1) && (sf_crtc->pp[pp_id].bus_out == 0))
 				return pp_id;
-			}
 		}
 	}
 
@@ -781,33 +779,34 @@ EXPORT_SYMBOL(starfive_pp_get_2lcdc_id);
 
 void dsitx_vout_init(struct starfive_crtc *sf_crtc)
 {
-	sf_set_clear(sf_crtc->toprst,rstgen_assert1_REG,(0x1&0x1)<<23,(0x1<<23));
-	sf_reg_status_wait(sf_crtc->toprst,rstgen_status1_REG,23,0);
-	sf_set_clear(sf_crtc->toprst,rstgen_assert1_REG,(0x1&0x1)<<24,(0x1<<24));
-	sf_reg_status_wait(sf_crtc->toprst,rstgen_status1_REG,24,0);
-	sf_set_clear(sf_crtc->topclk,clk_disp_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->topclk,clk_vout_src_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->toprst,rstgen_assert1_REG,(0x0&0x1)<<23,(0x1<<23));
-	sf_reg_status_wait(sf_crtc->toprst,rstgen_status1_REG,23,1);
-	sf_set_clear(sf_crtc->toprst,rstgen_assert1_REG,(0x0&0x1)<<24,(0x1<<24));
-	sf_reg_status_wait(sf_crtc->toprst,rstgen_status1_REG,24,1);
-	sf_set_clear(sf_crtc->base_clk,clk_disp0_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_disp1_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_lcdc_oclk_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_lcdc_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_vpp0_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_vpp1_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_vpp2_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_ppi_tx_esc_clk_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_dsi_apb_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_dsi_sys_clk_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-
-	sf_set_clear(sf_crtc->base_rst,vout_rstgen_assert0_REG,~0x1981ec,0x1981ec);
-		u32 temp;
-		do {
-			temp = ioread32(sf_crtc->base_rst+vout_rstgen_status0_REG);
-			temp &= 0x1981ec;
-		} while(temp!=0x1981ec);
+	sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, (0x1&0x1)<<23, (0x1<<23));
+	sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 0);
+	sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, (0x1&0x1)<<24, (0x1<<24));
+	sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 0);
+	sf_set_clear(sf_crtc->topclk, clk_disp_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->topclk, clk_vout_src_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, (0x0&0x1)<<23, (0x1<<23));
+	sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 1);
+	sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, (0x0&0x1)<<24, (0x1<<24));
+	sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 1);
+	sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_oclk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp0_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp1_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp2_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_ppi_tx_esc_clk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_apb_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_sys_clk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+
+	sf_set_clear(sf_crtc->base_rst, vout_rstgen_assert0_REG, ~0x1981ec, 0x1981ec);
+	u32 temp;
+
+	do {
+		temp = ioread32(sf_crtc->base_rst + vout_rstgen_status0_REG);
+		temp &= 0x1981ec;
+	} while (temp != 0x1981ec);
 }
 EXPORT_SYMBOL(dsitx_vout_init);
 
@@ -815,38 +814,39 @@ void vout_reset(struct starfive_crtc *sf_crtc)
 {
 	iowrite32(0xFFFFFFFF, sf_crtc->base_rst);
 
-	sf_set_clear(sf_crtc->topclk,clk_disp_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->topclk,clk_vout_src_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-
-	sf_set_clear(sf_crtc->toprst,rstgen_assert1_REG,(0x0&0x1)<<23,(0x1<<23));
-	sf_reg_status_wait(sf_crtc->toprst,rstgen_status1_REG,23,1);
-
-	sf_set_clear(sf_crtc->toprst,rstgen_assert1_REG,(0x0&0x1)<<24,(0x1<<24));
-	sf_reg_status_wait(sf_crtc->toprst,rstgen_status1_REG,24,1);
-
-	sf_set_clear(sf_crtc->base_clk,clk_disp0_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_disp1_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_lcdc_oclk_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_lcdc_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_vpp0_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_vpp1_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_vpp2_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_mapconv_apb_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_mapconv_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_pixrawout_apb_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_pixrawout_axi_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_csi2tx_strm0_apb_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_csi2tx_strm0_pixclk_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_ppi_tx_esc_clk_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_dsi_apb_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->base_clk,clk_dsi_sys_clk_ctrl_REG,(0x1&0x1)<<31,(0x1<<31));
-
-	sf_set_clear(sf_crtc->base_rst,vout_rstgen_assert0_REG,~0x19bfff,0x19bfff);
-	 u32 temp;
-	 do {
-		temp = ioread32(sf_crtc->base_rst+vout_rstgen_status0_REG);
+	sf_set_clear(sf_crtc->topclk, clk_disp_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->topclk, clk_vout_src_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+
+	sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, (0x0&0x1)<<23, (0x1<<23));
+	sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 1);
+
+	sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, (0x0&0x1)<<24, (0x1<<24));
+	sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 1);
+
+	sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_oclk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp0_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp1_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp2_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_mapconv_apb_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_mapconv_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_pixrawout_apb_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_pixrawout_axi_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_csi2tx_strm0_apb_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_csi2tx_strm0_pixclk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_ppi_tx_esc_clk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_apb_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_sys_clk_ctrl_REG, (0x1&0x1)<<31, (0x1<<31));
+
+	sf_set_clear(sf_crtc->base_rst, vout_rstgen_assert0_REG, ~0x19bfff, 0x19bfff);
+	u32 temp;
+
+	do {
+		temp = ioread32(sf_crtc->base_rst + vout_rstgen_status0_REG);
 		temp &= 0x19bfff;
-	} while(temp!=0x19bfff);
+	} while (temp != 0x19bfff);
 
 }
 EXPORT_SYMBOL(vout_reset);
@@ -855,14 +855,14 @@ void vout_disable(struct starfive_crtc *sf_crtc)
 {
 	iowrite32(0xFFFFFFFF, sf_crtc->base_rst);
 
-	sf_set_clear(sf_crtc->topclk,clk_disp_axi_ctrl_REG,(0x0&0x1)<<31,(0x1<<31));
-	sf_set_clear(sf_crtc->topclk,clk_vout_src_ctrl_REG,(0x0&0x1)<<31,(0x1<<31));
+	sf_set_clear(sf_crtc->topclk, clk_disp_axi_ctrl_REG, (0x0&0x1)<<31, (0x1<<31));
+	sf_set_clear(sf_crtc->topclk, clk_vout_src_ctrl_REG, (0x0&0x1)<<31, (0x1<<31));
 
-	sf_set_clear(sf_crtc->toprst,rstgen_assert1_REG,(0x1&0x1)<<23,(0x1<<23));
-	sf_reg_status_wait(sf_crtc->toprst,rstgen_status1_REG,23,0);
+	sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, (0x1&0x1)<<23, (0x1<<23));
+	sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 23, 0);
 
-	sf_set_clear(sf_crtc->toprst,rstgen_assert1_REG,(0x1&0x1)<<24,(0x1<<24));
-	sf_reg_status_wait(sf_crtc->toprst,rstgen_status1_REG,24,0);
+	sf_set_clear(sf_crtc->toprst, rstgen_assert1_REG, (0x1&0x1)<<24, (0x1<<24));
+	sf_reg_status_wait(sf_crtc->toprst, rstgen_status1_REG, 24, 0);
 }
 EXPORT_SYMBOL(vout_disable);
 
diff --git a/drivers/gpu/drm/starfive/starfive_drm_vpp.h b/drivers/gpu/drm/starfive/starfive_drm_vpp.h
index fb69049ca621..9cb222f35e15 100755
--- a/drivers/gpu/drm/starfive/starfive_drm_vpp.h
+++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.h
@@ -23,7 +23,6 @@
 #define PP_INTR_ENABLE	1
 #define PP_INTR_DISABLE	0
 //PP coefficients
-///*
 #define R2Y_COEF_R1       77
 #define R2Y_COEF_G1       150
 #define R2Y_COEF_B1       29
@@ -38,46 +37,42 @@
 #define R2Y_COEF_G3       (0x400|107)
 #define R2Y_COEF_B3       (0x400|21)
 #define R2Y_OFFSET3       128
-//*/
-enum PP_LCD_PATH
-{
-    SYS_BUS_OUTPUT = 0,
-    FIFO_OUTPUT = 1,
+
+enum PP_LCD_PATH {
+	SYS_BUS_OUTPUT = 0,
+	FIFO_OUTPUT = 1,
 };
 
-enum PP_COLOR_CONVERT_SCALE
-{
-    NOT_BYPASS = 0,
-    BYPASS,
+enum PP_COLOR_CONVERT_SCALE {
+	NOT_BYPASS = 0,
+	BYPASS,
 };
 
-enum PP_SRC_FORMAT
-{
-    PP_SRC_YUV420P = 0,
-    PP_SRC_YUV422,
-    PP_SRC_YUV420I,
-    PP_RESERVED,
-    PP_SRC_GRB888,
-    PP_SRC_RGB565,
+enum PP_SRC_FORMAT {
+	PP_SRC_YUV420P = 0,
+	PP_SRC_YUV422,
+	PP_SRC_YUV420I,
+	PP_RESERVED,
+	PP_SRC_GRB888,
+	PP_SRC_RGB565,
 };
 
-enum PP_DST_FORMAT
-{
-    PP_DST_YUV420P = 0,
-    PP_DST_YUV422,
-    PP_DST_YUV420I,
-    PP_DST_RGBA888,
-    PP_DST_ARGB888,
-    PP_DST_RGB565,
-    PP_DST_ABGR888,
-    PP_DST_BGRA888,
+enum PP_DST_FORMAT {
+	PP_DST_YUV420P = 0,
+	PP_DST_YUV422,
+	PP_DST_YUV420I,
+	PP_DST_RGBA888,
+	PP_DST_ARGB888,
+	PP_DST_RGB565,
+	PP_DST_ABGR888,
+	PP_DST_BGRA888,
 };
 
 
 struct pp_video_mode {
-    enum COLOR_FORMAT format;
-    unsigned int height;
-    unsigned int width;
+	enum COLOR_FORMAT format;
+	unsigned int height;
+	unsigned int width;
 	unsigned int addr;
 };
 
@@ -168,12 +163,12 @@ struct pp_mode {
 //for vout reg
 #define CLKGEN_BASE_ADDR                0x11800000
 
-#define clk_disp_axi_ctrl_REG   	 0x1C0
-#define clk_vout_src_ctrl_REG   	 0x1B4
-#define rstgen_assert1_REG           0x4
-#define rstgen_status1_REG           0x14
-#define vout_rstgen_assert0_REG    		0x0
-#define vout_rstgen_status0_REG    		0x4
+#define clk_disp_axi_ctrl_REG		0x1C0
+#define clk_vout_src_ctrl_REG		0x1B4
+#define rstgen_assert1_REG			0x4
+#define rstgen_status1_REG			0x14
+#define vout_rstgen_assert0_REG		0x0
+#define vout_rstgen_status0_REG		0x4
 #define clk_vout_apb_ctrl_REG       0x0
 #define clk_mapconv_apb_ctrl_REG    0x4
 #define clk_mapconv_axi_ctrl_REG    0x8
@@ -184,13 +179,13 @@ struct pp_mode {
 #define clk_vpp0_axi_ctrl_REG       0x1C
 #define clk_vpp1_axi_ctrl_REG       0x20
 #define clk_vpp2_axi_ctrl_REG       0x24
-#define clk_pixrawout_apb_ctrl_REG    		0x28
-#define clk_pixrawout_axi_ctrl_REG    		0x2C
-#define clk_csi2tx_strm0_pixclk_ctrl_REG    0x30
-#define clk_csi2tx_strm0_apb_ctrl_REG    	0x34
-#define clk_dsi_sys_clk_ctrl_REG    		0x38
-#define clk_dsi_apb_ctrl_REG    			0x3C
-#define clk_ppi_tx_esc_clk_ctrl_REG   		0x40
+#define clk_pixrawout_apb_ctrl_REG			0x28
+#define clk_pixrawout_axi_ctrl_REG			0x2C
+#define clk_csi2tx_strm0_pixclk_ctrl_REG	0x30
+#define clk_csi2tx_strm0_apb_ctrl_REG		0x34
+#define clk_dsi_sys_clk_ctrl_REG			0x38
+#define clk_dsi_apb_ctrl_REG				0x3C
+#define clk_ppi_tx_esc_clk_ctrl_REG			0x40
 
 extern void mapconv_pp0_sel(struct starfive_crtc *sf_crtc, int sel);
 extern void pp_srcAddr_next(struct starfive_crtc *sf_crtc, int ppNum, int ysa, int usa, int vsa);