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| author | andy.hu <andy.hu@starfivetech.com> | 2023-08-03 14:27:28 +0300 |
|---|---|---|
| committer | andy.hu <andy.hu@starfivetech.com> | 2023-08-03 14:27:28 +0300 |
| commit | 206e29e82f591a73421865800082e287caead9d2 (patch) | |
| tree | d6440e00e6437b2a3a6e4400f54e5332a0afe5e5 | |
| parent | 67be5517e9315d9fdb334bda450f8b86f5bc101b (diff) | |
| parent | 4a10b176dbc6063f68cdb2ec9ac7673a05b1e476 (diff) | |
| download | linux-206e29e82f591a73421865800082e287caead9d2.tar.xz | |
Merge branch 'CR_6570_SDBOOT_6.1_william.qiu' into 'vf2-6.1.y-devel'
CR_6570_6.1 : riscv: dts: starfive: limit cclk in frequency
See merge request sbc/linux!150
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi index 8a70ae5ccd5c..a1bda809cd37 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi @@ -648,9 +648,12 @@ &mmc0 { max-frequency = <100000000>; + assigned-clocks = <&clkgen JH7110_SDIO0_CLK_SDCARD>; + assigned-clock-rates = <50000000>; card-detect-delay = <300>; bus-width = <8>; cap-mmc-highspeed; + mmc-hs200-1_8v; non-removable; cap-mmc-hw-reset; post-power-on-delay-ms = <200>; @@ -661,6 +664,8 @@ &mmc1 { max-frequency = <100000000>; + assigned-clocks = <&clkgen JH7110_SDIO1_CLK_SDCARD>; + assigned-clock-rates = <50000000>; card-detect-delay = <300>; bus-width = <4>; no-sdio; |