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| author | xingyu.wu <xingyu.wu@starfivetech.com> | 2021-12-31 12:48:22 +0300 |
|---|---|---|
| committer | xingyu.wu <xingyu.wu@starfivetech.com> | 2022-01-04 18:12:38 +0300 |
| commit | 29386f3be40fa43ecc88c958d32a0dc2cf3d07d2 (patch) | |
| tree | 0349d825e5da1c6ad6e12019684e285710a56939 | |
| parent | 32f645aaf3b1fb8c47ae9dfb50a6ab642b6fa5b4 (diff) | |
| download | linux-29386f3be40fa43ecc88c958d32a0dc2cf3d07d2.tar.xz | |
dts: starfive: Amend Vdec module device tree
Add clock and reset nodes in Vdec module device tree.
Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
| -rwxr-xr-x[-rw-r--r--] | arch/riscv/boot/dts/starfive/jh7100.dtsi | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 48f87141f00e..fe8b911470cf 100644..100755 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -407,8 +407,18 @@ vpu_dec: vpu_dec@118f0000 { compatible = "c&m,cm511-vpu"; reg = <0 0x118f0000 0 0x10000>; - clocks = <&clkgen JH7100_CLK_VP6_CORE>; - clock-names = "vcodec"; + clocks =<&clkgen JH7100_CLK_VDEC_AXI>, + <&clkgen JH7100_CLK_VDECBRG_MAIN>, + <&clkgen JH7100_CLK_VDEC_BCLK>, + <&clkgen JH7100_CLK_VDEC_CCLK>, + <&clkgen JH7100_CLK_VDEC_APB>; + clock-names = "vdec_axi", "vdecbrg_main", "vdec_bclk", "vdec_cclk", "vdec_apb"; + resets = <&rstgen JH7100_RSTN_VDEC_AXI>, + <&rstgen JH7100_RSTN_VDECBRG_MAIN>, + <&rstgen JH7100_RSTN_VDEC_BCLK>, + <&rstgen JH7100_RSTN_VDEC_CCLK>, + <&rstgen JH7100_RSTN_VDEC_APB>; + reset-names = "vdec_axi", "vdecbrg_main", "vdec_bclk", "vdec_cclk", "vdec_apb"; interrupts = <23>; //memory-region = <&vpu_reserved>; }; |