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| author | Andy Hu <andy.hu@starfivetech.com> | 2024-06-21 12:31:05 +0300 |
|---|---|---|
| committer | Andy Hu <andy.hu@starfivetech.com> | 2024-06-21 12:31:05 +0300 |
| commit | fd29ad18c668c03a3c688c645ef9ba7c1c3ad286 (patch) | |
| tree | 3b6a996f6221fc4bad2b45625f0276ae3a68259e | |
| parent | 7fc8a72478dcc7420e3633ea8bc9b82001a847a9 (diff) | |
| parent | ea9fba1d65c5662765794491b93b63cbbf033bc0 (diff) | |
| download | linux-fd29ad18c668c03a3c688c645ef9ba7c1c3ad286.tar.xz | |
Merge tag 'JH7110_SDK_6.6_v5.12.3' into vf2-6.6.y-devel
| -rw-r--r-- | drivers/net/phy/motorcomm.c | 15 | ||||
| -rw-r--r-- | drivers/spi/spi-pl022.c | 4 |
2 files changed, 15 insertions, 4 deletions
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 7a11fdb687cc..6bc3333b76dc 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -792,7 +792,7 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) { int tb_size = ARRAY_SIZE(ytphy_rgmii_delays); u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN; - u32 rx_reg, tx_reg; + u32 rx_reg, tx_reg, tx_fe_reg; u16 mask, val = 0; int ret; @@ -804,6 +804,10 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) ytphy_rgmii_delays, tb_size, NULL, YT8521_RC1R_RGMII_1_950_NS); + tx_fe_reg = ytphy_get_delay_reg_value(phydev, "tx-fe-internal-delay-ps", + ytphy_rgmii_delays, tb_size, NULL, + YT8521_RC1R_RGMII_0_000_NS); + switch (phydev->interface) { case PHY_INTERFACE_MODE_RGMII: rxc_dly_en = 0; @@ -813,11 +817,13 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) break; case PHY_INTERFACE_MODE_RGMII_TXID: rxc_dly_en = 0; - val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); + val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg) | + FIELD_PREP(YT8521_RC1R_FE_TX_DELAY_MASK, tx_fe_reg); break; case PHY_INTERFACE_MODE_RGMII_ID: val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) | - FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); + FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg) | + FIELD_PREP(YT8521_RC1R_FE_TX_DELAY_MASK, tx_fe_reg); break; default: /* do not support other modes */ return -EOPNOTSUPP; @@ -828,8 +834,9 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) if (ret < 0) return ret; + mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK | /* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */ - mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK; + YT8521_RC1R_FE_TX_DELAY_MASK; return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val); } diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index 1420c40fa815..1189b484b4f1 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c @@ -1803,6 +1803,10 @@ static int calculate_effective_freq(struct pl022 *pl022, int freq, struct WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", freq); + if (best_freq != freq) + dev_warn(&pl022->adev->dev, + "Requested frequency: %d Hz is unsupported,select by default %d Hz\n", + freq, best_freq); clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); clk_freq->scr = (u8) (best_scr & 0xFF); dev_dbg(&pl022->adev->dev, |