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| author | andy.hu <andy.hu@starfivetech.com> | 2024-01-05 09:07:04 +0300 |
|---|---|---|
| committer | andy.hu <andy.hu@starfivetech.com> | 2024-01-05 09:07:04 +0300 |
| commit | bb509f27e05139f715c9cf16819903b120a63bb6 (patch) | |
| tree | 93a032841085bdfa572c77a9132c78ca07480fe5 | |
| parent | 7ad9e62e93481d0356efd7c4e399959ba7cbe8ee (diff) | |
| parent | fd1ae6c74add0ef474383437378d3bca9345133e (diff) | |
| download | linux-bb509f27e05139f715c9cf16819903b120a63bb6.tar.xz | |
Merge branch 'CR_8759_6_1_DRM_MIPI_PANEL_keith.zhao' into 'jh7110-6.1.y-devel'
CR 8759: dts:mipi: clocks re-match
See merge request sdk/linux!999
| -rwxr-xr-x[-rw-r--r--] | arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/verisilicon/starfive_drm_dsi.c | 27 |
2 files changed, 19 insertions, 10 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 7804faed050b..19928efe3b1a 100644..100755 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -1535,7 +1535,7 @@ <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>, <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>, <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>; - clock-names = "sys", "apb", "txesc", "dpi"; + clock-names = "dpi", "apb", "txesc", "sys"; resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>, <&rstgen RSTN_U0_CDNS_DSITX_APB>, <&rstgen RSTN_U0_CDNS_DSITX_RXESC>, diff --git a/drivers/gpu/drm/verisilicon/starfive_drm_dsi.c b/drivers/gpu/drm/verisilicon/starfive_drm_dsi.c index 6cb8ba3e2a57..104fe10624f3 100644 --- a/drivers/gpu/drm/verisilicon/starfive_drm_dsi.c +++ b/drivers/gpu/drm/verisilicon/starfive_drm_dsi.c @@ -746,13 +746,7 @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, bpp, 0); dsi_cfg->hfp = dpi_to_dsi_timing(mode_to_dpi_hfp(mode, mode_valid_check), bpp, DSI_HFP_FRAME_OVERHEAD); - //dpi to dsi transfer can not match , reconfig those parms for waveshare - //for taobao old mipi panel .should change here : hsa 36 , hbp 108, hfp 288 - if (mode->hdisplay == 800) { - dsi_cfg->hsa = 117-DSI_HSA_FRAME_OVERHEAD; - dsi_cfg->hbp = 115-DSI_HBP_FRAME_OVERHEAD; - dsi_cfg->hfp = 209-DSI_HFP_FRAME_OVERHEAD; - } + return 0; } @@ -785,6 +779,7 @@ static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi, * misalignment. */ adj_dsi_htotal = dsi_htotal; + if (dsi_htotal % lanes) adj_dsi_htotal += lanes - (dsi_htotal % lanes); @@ -794,10 +789,22 @@ static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi, /* data rate in bytes/sec is not an integer, refuse the mode. */ dpi_htotal = mode_valid_check ? mode->htotal : mode->crtc_htotal; + if (do_div(dlane_bps, lanes * dpi_htotal)) + return -EINVAL; + /* data rate was in bytes/sec, convert to bits/sec. */ - phy_cfg->hs_clk_rate = 750000000; + phy_cfg->hs_clk_rate = dlane_bps * 8; + phy_cfg->hs_clk_rate = phy_cfg->hs_clk_rate - (phy_cfg->hs_clk_rate % 10000000); + phy_cfg->hs_clk_rate = phy_cfg->hs_clk_rate + 10000000; + printk("%s,hs_clk_rate %ld\n",__func__,phy_cfg->hs_clk_rate); + + dlane_bps = phy_cfg->hs_clk_rate * lanes * dpi_htotal / 8; + + adj_dsi_htotal = dlane_bps/dpi_hz; dsi_hfp_ext = adj_dsi_htotal - dsi_htotal; + + printk("%s,dsi_hfp_ext %d\n",__func__,dsi_hfp_ext); dsi_cfg->hfp += dsi_hfp_ext; dsi_cfg->htotal = dsi_htotal + dsi_hfp_ext; @@ -832,7 +839,9 @@ static int cdns_dsi_check_conf(struct cdns_dsi *dsi, if (ret) return ret; - phy_cfg->hs_clk_rate = 750000000; + dsi_cfg->htotal = dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD + + dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD + + dsi_cfg->hfp + DSI_HFP_FRAME_OVERHEAD + dsi_cfg->hact; dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD; if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) |