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| author | jianlong.huang <jianlong.huang@starfivetech.com> | 2022-06-13 10:45:47 +0300 |
|---|---|---|
| committer | jianlong.huang <jianlong.huang@starfivetech.com> | 2022-06-13 10:45:47 +0300 |
| commit | 87c5a26057fdbc77da7019e672cd28a263bb33f8 (patch) | |
| tree | 06dd8457f7e14d2826f94280ee882c5048f8b4b0 | |
| parent | b9eafe98ae283ec3733cccc8cfe9cee0cca7e48e (diff) | |
| parent | 6d2ff952d11b191d405351ad80c38750700fbb66 (diff) | |
| download | linux-87c5a26057fdbc77da7019e672cd28a263bb33f8.tar.xz | |
Merge branch 'CR_1105_VPUJPU_Som.Qin' into 'JH7100_VisionFive_OH_dev'
Cr 1105 vpujpu som.qin
See merge request jh7100/linux!41
| -rwxr-xr-x | arch/riscv/boot/dts/starfive/jh7100.dtsi | 40 |
1 files changed, 34 insertions, 6 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 19a0027204bf..1b9e898689d2 100755 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -447,16 +447,36 @@ compatible = "cm,cm521-vpu"; reg = <0x0 0x118e0000 0x0 0x4000>; reg-names = "control"; - clocks = <&clkgen JH7100_CLK_VP6_CORE>; - clock-names = "vcodec"; + clocks =<&clkgen JH7100_CLK_VENC_AXI>, + <&clkgen JH7100_CLK_VENCBRG_MAIN>, + <&clkgen JH7100_CLK_VENC_BCLK>, + <&clkgen JH7100_CLK_VENC_CCLK>, + <&clkgen JH7100_CLK_VENC_APB>; + clock-names = "venc_axi", "vencbrg_main", "venc_bclk", "venc_cclk", "venc_apb"; + resets = <&rstgen JH7100_RSTN_VENC_AXI>, + <&rstgen JH7100_RSTN_VENCBRG_MAIN>, + <&rstgen JH7100_RSTN_VENC_BCLK>, + <&rstgen JH7100_RSTN_VENC_CCLK>, + <&rstgen JH7100_RSTN_VENC_APB>; + reset-names = "venc_axi", "vencbrg_main", "venc_bclk", "venc_cclk", "venc_apb"; interrupts = <26>; }; vpu_dec: vpu_dec@118f0000 { compatible = "c&m,cm511-vpu"; reg = <0 0x118f0000 0 0x10000>; - clocks = <&clkgen JH7100_CLK_VP6_CORE>; - clock-names = "vcodec"; + clocks =<&clkgen JH7100_CLK_VDEC_AXI>, + <&clkgen JH7100_CLK_VDECBRG_MAIN>, + <&clkgen JH7100_CLK_VDEC_BCLK>, + <&clkgen JH7100_CLK_VDEC_CCLK>, + <&clkgen JH7100_CLK_VDEC_APB>; + clock-names = "vdec_axi", "vdecbrg_main", "vdec_bclk", "vdec_cclk", "vdec_apb"; + resets = <&rstgen JH7100_RSTN_VDEC_AXI>, + <&rstgen JH7100_RSTN_VDECBRG_MAIN>, + <&rstgen JH7100_RSTN_VDEC_BCLK>, + <&rstgen JH7100_RSTN_VDEC_CCLK>, + <&rstgen JH7100_RSTN_VDEC_APB>; + reset-names = "vdec_axi", "vdecbrg_main", "vdec_bclk", "vdec_cclk", "vdec_apb"; interrupts = <23>; //memory-region = <&vpu_reserved>; }; @@ -465,8 +485,16 @@ compatible = "cm,codaj12-jpu-1"; reg = <0x0 0x11900000 0x0 0x300>; reg-names = "control"; - clocks = <&clkgen JH7100_CLK_JPEG_APB>; - clock-names = "jpege"; + clocks = <&clkgen JH7100_CLK_JPEG_AXI>, + <&clkgen JH7100_CLK_JPEG_CCLK>, + <&clkgen JH7100_CLK_JPEG_APB>, + <&clkgen JH7100_CLK_VDECBRG_MAIN>, + <&clkgen JH7100_CLK_JPCGC300_MAIN>; + clock-names = "jpeg_axi", "jpeg_cclk", "jpeg_apb", "vdecbrg_main", "jpcgc300_main"; + resets = <&rstgen JH7100_RSTN_JPEG_AXI>, + <&rstgen JH7100_RSTN_JPEG_CCLK>, + <&rstgen JH7100_RSTN_JPEG_APB>; + reset-names = "jpeg_axi", "jpeg_cclk", "jpeg_apb"; interrupts = <24>; memory-region = <&jpu_reserved>; }; |