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| author | Rhyland Klein <rklein@nvidia.com> | 2016-03-21 22:58:52 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 13:41:50 +0300 |
| commit | 926655f929063619b13db8b4f2ef8c9a08605492 (patch) | |
| tree | ffcb529ae83a81e7840b9f57ccf11006fb15fd56 /.get_maintainer.ignore | |
| parent | a91bb605ec5f93676e503267c89469d02c5b4cbc (diff) | |
| download | linux-926655f929063619b13db8b4f2ef8c9a08605492.tar.xz | |
clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Use a new Tegra210 version of the pll_register_pllre function to
allow setting the proper settings for the m and n div fields.
Additionally define PLL_RE_OUT1 on Tegra210.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[treding@nvidia.com: define PLLRE_OUT1 register offset]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to '.get_maintainer.ignore')
0 files changed, 0 insertions, 0 deletions