StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) https://git.radix-linux.su/starfive-tech/linux.git/atom?h=visionfive 2025-08-10T06:02:36+00:00 2025-08-10T06:02:36+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-08-10T06:02:36+00:00 urn:sha1:2b38afce25c4e1b8f943ff4f0a2b51d6c40f2ed2 Pull turbostat updates from Len Brown: "tools/power turbostat: version 2025.09.09 - Probe and display L3 Cache topology - Add ability to average an added counter (useful for pre-integrated "counters", such as Watts) - Break the limit of 64 built-in counters - Assorted bug fixes and minor feature tweaks" * tag 'turbostat-2025.09.09' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux: tools/power turbostat: version 2025.09.09 tools/power turbostat: Handle non-root legacy-uncore sysfs permissions tools/power turbostat: standardize PER_THREAD_PARAMS tools/power turbostat: Fix DMR support tools/power turbostat: add format "average" for external attributes tools/power turbostat: delete GET_PKG() tools/power turbostat: probe and display L3 cache topology tools/power turbostat: Support more than 64 built-in-counters tools/power turbostat.8: Document Totl%C0, Any%C0, GFX%C0, CPUGFX% columns tools/power turbostat: Fix bogus SysWatt for forked program tools/power turbostat: Handle cap_get_proc() ENOSYS tools/power turbostat: Fix build with musl tools/power turbostat: verify arguments to params --show and --hide tools/power turbostat: regression fix: --show C1E% 2025-08-10T01:24:46+00:00 Len Brown len.brown@intel.com 2025-08-10T01:08:26+00:00 urn:sha1:5e98a5e73edcc4114c5ad10596db87e24f50ee4d Probe and display L3 Cache topology Add ability to average an added counter (useful for pre-integrated "counters", such as Watts) Break the limit of 64 built-in counters. Assorted bug fixes and minor feature tweaks Signed-off-by: Len Brown <len.brown@intel.com> 2025-08-10T01:24:46+00:00 Len Brown len.brown@intel.com 2025-08-09T20:31:31+00:00 urn:sha1:e60a13bcef206795d3ddf82f130fe8f570176d06 /sys/devices/system/cpu/intel_uncore_frequency/package_X_die_Y/ may be readable by all, but /sys/devices/system/cpu/intel_uncore_frequency/package_X_die_Y/current_freq_khz may be readable only by root. Non-root turbostat users see complaints in this scenario. Fail probe of the interface if we can't read current_freq_khz. Reported-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Original-patch-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> 2025-08-10T01:24:46+00:00 Len Brown len.brown@intel.com 2025-08-08T23:30:07+00:00 urn:sha1:378e901160256d2ab66e45ffb97afaca51e65706 use a macro for PER_THREAD_PARAMS to make adding one later more clear. no functional change Signed-off-by: Len Brown <len.brown@intel.com> 2025-08-10T01:24:46+00:00 Zhang Rui rui.zhang@intel.com 2025-06-11T06:50:26+00:00 urn:sha1:3a088b07c4f10bf577f4a2392111704195a794ba Together with the RAPL MSRs, there are more MSRs gone on DMR, including PLR (Perf Limit Reasons), and IRTL (Package cstate Interrupt Response Time Limit) MSRs. The configurable TDP info should also be retrieved from TPMI based Intel Speed Select Technology feature. Remove the access of these MSRs for DMR. Improve the DMR platform feature table to make it more readable at the same time. Fixes: 83075bd59de2 ("tools/power turbostat: Add initial support for DMR") Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> 2025-08-10T01:24:46+00:00 Michael Hebenstreit michael.hebenstreit@intel.com 2025-08-08T19:57:53+00:00 urn:sha1:dcd1c379b0f179763956e8596ad99912165a95ec External atributes with format "raw" are not printed in summary lines for nodes/packages (or with option -S). The new format "average" behaves like "raw" but also adds the summary data Signed-off-by: Michael Hebenstreit <michael.hebenstreit@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> 2025-08-10T01:24:46+00:00 Len Brown len.brown@intel.com 2025-07-22T04:17:04+00:00 urn:sha1:a5015d945de6003cf813af2bb11189982f5b3d54 pkg_base[pkg_id] is a simple array of structure pointers, let the compiler treat it that way. Signed-off-by: Len Brown <len.brown@intel.com> 2025-08-10T01:24:46+00:00 Len Brown len.brown@intel.com 2025-07-15T03:33:55+00:00 urn:sha1:5f961fb2a7d8f4d89d64a9e2cd584738de5f9c58 Signed-off-by: Len Brown <len.brown@intel.com> 2025-08-10T01:23:45+00:00 Len Brown len.brown@intel.com 2025-07-12T20:16:56+00:00 urn:sha1:8d14a098b47cc7e5cfa703b9e015d6ca1074489a We have out-grown the ability to use a 64-bit memory location to inventory every possible built-in counter. Leverage the the CPU_SET(3) macros to break this barrier. Also, break the Joules & Watts counters into two, since we can no longer 'or' them together... Signed-off-by: Len Brown <len.brown@intel.com> 2025-08-09T15:14:30+00:00 Len Brown len.brown@intel.com 2025-06-23T20:24:25+00:00 urn:sha1:d240b441b5cbb389f90fce37edb9ef76a3c9a42b Explain the meaning of the Totl%C0, Any%C0, GFX%C0, CPUGFX% columns. Signed-off-by: Len Brown <len.brown@intel.com>