starfive-tech/linux.git/include, branch JH7110_VisionFive2_multi_rtosStarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)https://git.radix-linux.su/starfive-tech/linux.git/atom?h=JH7110_VisionFive2_multi_rtos2024-12-06T06:02:51+00:00driver: mipi : test tool2024-12-06T06:02:51+00:00keith.zhaokeith.zhao@starfivetech.com2024-10-08T02:43:35+00:00urn:sha1:90f1c590417c964455cd8c912f3384bab7ae12dc
update mipi driver support mipi test tool
Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
virtio: Add a new event queue allocate function.2024-05-31T09:29:07+00:00Minda Chenminda.chen@starfivetech.com2024-05-13T08:49:27+00:00urn:sha1:62f6dc972e3782aaad5731d22974ed747f46f021
Add a new event queue allocate function which will call a self-defined
event queue init callback. new queue init callback function can set
cache line align, which can reduce the snoop invalidate dcache line in
IPI AMP communication.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
media: v4l2: Add ignore_streaming flag2024-03-05T07:18:32+00:00Sebastian Frickesebastian.fricke@collabora.com2023-11-08T19:29:20+00:00urn:sha1:afd6a12713b7df6165ed3ce3b82e6a7f3202b3fb
Add a new flag to the `struct v4l2_m2m_dev` to toggle whether a queue
must be streaming in order to allow queuing jobs to the ready queue.
Currently, both queues (CAPTURE & OUTPUT) must be streaming in order to
allow adding new jobs. This behavior limits the usability of M2M for
some drivers, as these have to be able, to perform analysis of the
sequence to ensure, that userspace prepares the CAPTURE queue correctly.
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
riscv: cpu: cache: Implement a new method to flush the entire L2 cache2024-03-05T07:18:32+00:00Windsome Zengwindsome.zeng@starfivetech.com2024-01-11T10:29:10+00:00urn:sha1:38940b8f25fb1a645d7f3097491e68a17ca141b5
According to the manual of SiFive U74, implement a new method to flush the entire L2 cache by using the Zero Device.
After testing, 512KB is the critical point between the old and new way. It's better to use sifive_ccache_flush_entire
function while data size is larger than cache size. Or it will improve more at 512KB when you know what you are doing.
Signed-off-by: Windsome Zeng <windsome.zeng@starfivetech.com>
Add ISP control for video2 and video3.2024-03-05T07:18:32+00:00zejian.suzejian.su@starfivetech.com2023-10-30T08:09:58+00:00urn:sha1:cb7cf3eb97bca970034b9215254d6e3b2e8590ab
Signed-off-by: zejian.su <zejian.su@starfivetech.com>
Expand 2 bytes after the SC buffer for the AE/AWB flag and copy the histogram data to the SC buffer.2024-03-05T07:18:32+00:00zejian.suzejian.su@starfivetech.com2023-08-07T02:38:36+00:00urn:sha1:44f4b97811aab8e4c6b571e9d5255822ee5793a9Add 16 ISP controls, remove the frame SYNC event to video7 (SC) These controls are: WB, CAR, CCM, CFA, CTC, DBC, DNYUV, GMARGB, LCCF, OBC, OECF, R2Y, SAT, SHRP, YCRV, SC2024-03-05T07:18:32+00:00zejian.suzejian.su@starfivetech.com2023-07-03T08:52:13+00:00urn:sha1:cd77981d2174ca572112ea584d00cea8d1ebbab0soc: sifive: ccache: Add sifive_l2_flush64_range2024-03-05T07:18:31+00:00Samin Guosamin.guo@starfivetech.com2023-06-26T08:43:17+00:00urn:sha1:cadfdf82e63fed79500665e782af4241a1f5f0bf
Add sifive_l2_flush64_range to be compatible with old code
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
soc: sifive: ccache: Add non-coherent DMA handling2024-03-05T07:18:31+00:00Emil Renner Berthingkernel@esmil.dk2023-06-26T06:45:57+00:00urn:sha1:4b7881a978b3ee0a4f67b1d0e65cf7f097a4f370
Add functions to flush the caches and handle non-coherent DMA.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
workqueue: Enable flush_scheduled_work()2024-03-05T07:18:31+00:00Hal Fenghal.feng@starfivetech.com2023-12-12T09:56:58+00:00urn:sha1:d89c0fec5e542e859df5dc590caeaff99cae10db
Enable flush_scheduled_work() for JH7110 GPU.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>