<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/linux.git/include/linux, branch VF2_v3.4.5</title>
<subtitle>StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/linux.git/atom?h=VF2_v3.4.5</id>
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<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/'/>
<updated>2023-07-13T00:42:02+00:00</updated>
<entry>
<title>Merge tag 'JH7110_515_SDK_v5.4.0' into vf2-515-devel</title>
<updated>2023-07-13T00:42:02+00:00</updated>
<author>
<name>Andy Hu</name>
<email>andy.hu@starfivetech.com</email>
</author>
<published>2023-07-13T00:42:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=aa611547935bab2e31d94c457b918214ba48a1c0'/>
<id>urn:sha1:aa611547935bab2e31d94c457b918214ba48a1c0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>etherdevice: Adjust ether_addr* prototypes to silence -Wstringop-overead</title>
<updated>2023-07-10T07:17:14+00:00</updated>
<author>
<name>Kees Cook</name>
<email>keescook@chromium.org</email>
</author>
<published>2022-02-12T17:14:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=f5f5926a5fe160740ba8538997e575e752f20601'/>
<id>urn:sha1:f5f5926a5fe160740ba8538997e575e752f20601</id>
<content type='text'>
With GCC 12, -Wstringop-overread was warning about an implicit cast from
char[6] to char[8]. However, the extra 2 bytes are always thrown away,
alignment doesn't matter, and the risk of hitting the edge of unallocated
memory has been accepted, so this prototype can just be converted to a
regular char *. Silences:

net/core/dev.c: In function ‘bpf_prog_run_generic_xdp’: net/core/dev.c:4618:21: warning: ‘ether_addr_equal_64bits’ reading 8 bytes from a region of size 6 [-Wstringop-overread]
 4618 |         orig_host = ether_addr_equal_64bits(eth-&gt;h_dest, &gt; skb-&gt;dev-&gt;dev_addr);
      |                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
net/core/dev.c:4618:21: note: referencing argument 1 of type ‘const u8[8]’ {aka ‘const unsigned char[8]’}
net/core/dev.c:4618:21: note: referencing argument 2 of type ‘const u8[8]’ {aka ‘const unsigned char[8]’}
In file included from net/core/dev.c:91: include/linux/etherdevice.h:375:20: note: in a call to function ‘ether_addr_equal_64bits’
  375 | static inline bool ether_addr_equal_64bits(const u8 addr1[6+2],
      |                    ^~~~~~~~~~~~~~~~~~~~~~~

Reported-by: Marc Kleine-Budde &lt;mkl@pengutronix.de&gt;
Tested-by: Marc Kleine-Budde &lt;mkl@pengutronix.de&gt;
Link: https://lore.kernel.org/netdev/20220212090811.uuzk6d76agw2vv73@pengutronix.de
Cc: Jakub Kicinski &lt;kuba@kernel.org&gt;
Cc: "David S. Miller" &lt;davem@davemloft.net&gt;
Cc: netdev@vger.kernel.org
Signed-off-by: Kees Cook &lt;keescook@chromium.org&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>Merge tag 'JH7110_515_SDK_v5.3.0' into vf2-515-devel</title>
<updated>2023-06-28T09:55:01+00:00</updated>
<author>
<name>Andy Hu</name>
<email>andy.hu@starfivetech.com</email>
</author>
<published>2023-06-28T09:55:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=22bc1c3edae297432eb51fd4216bec01581f9e0d'/>
<id>urn:sha1:22bc1c3edae297432eb51fd4216bec01581f9e0d</id>
<content type='text'>
</content>
</entry>
<entry>
<title>uart: 8250: Add dw auto flow ctrl support</title>
<updated>2023-06-25T02:04:02+00:00</updated>
<author>
<name>Minda Chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-06-25T01:40:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=235c08ba9240439c00d55897f57126cb8438a38c'/>
<id>urn:sha1:235c08ba9240439c00d55897f57126cb8438a38c</id>
<content type='text'>
Add designeware 8250 auto flow ctrl support. Enable
it by add auto-flow-control in dts.

Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>regulator: axp15060: enbale ALDO4 and DCDC1</title>
<updated>2023-04-13T03:27:39+00:00</updated>
<author>
<name>William Qiu</name>
<email>william.qiu@starfivetech.com</email>
</author>
<published>2023-04-13T03:27:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=905e8cbff6516b8ac7309229ecbb361622e86645'/>
<id>urn:sha1:905e8cbff6516b8ac7309229ecbb361622e86645</id>
<content type='text'>
enbale ALDO4 for the MMC bus IO line power and DCDC1 the card power

Signed-off-by: William Qiu &lt;william.qiu@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'JH7110_515_SDK_v4.0.0-rc1' into vf2-515-devel</title>
<updated>2023-01-07T15:02:18+00:00</updated>
<author>
<name>Andy Hu</name>
<email>andy.hu@starfivetech.com</email>
</author>
<published>2023-01-07T15:02:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=50a831018ed997c9fb3b603574176b221a28aa12'/>
<id>urn:sha1:50a831018ed997c9fb3b603574176b221a28aa12</id>
<content type='text'>
version JH7110_515_SDK_v4.0.0-rc1 for JH7110 EVB board
1. #2828 support linux perf tool
2. #3049 merge hibernation branch to SDK
3. #2708 uboot support vout clk driver
4. #3006 uboot handle OTP return value
5. #2969, #3039 venc jpu fix futex issue
</content>
</entry>
<entry>
<title>RISC-V: Add sscofpmf extension support</title>
<updated>2023-01-03T06:26:17+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2021-08-27T22:03:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=f90b5c68dcce615739e533ad306be090ca1c99a1'/>
<id>urn:sha1:f90b5c68dcce615739e533ad306be090ca1c99a1</id>
<content type='text'>
The sscofpmf extension allows counter overflow and filtering for
programmable counters. Enable the perf driver to handle the overflow
interrupt. The overflow interrupt is a hart local interrupt.
Thus, per cpu overflow interrupts are setup as a child under the root
INTC irq domain.

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Add perf platform driver based on SBI PMU extension</title>
<updated>2023-01-03T06:26:17+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2021-03-17T23:54:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=9a7e4fe5717564dfbd317990b50eddb42bb36ae8'/>
<id>urn:sha1:9a7e4fe5717564dfbd317990b50eddb42bb36ae8</id>
<content type='text'>
RISC-V SBI specification added a PMU extension that allows to configure
start/stop any pmu counter. The RISC-V perf can use most of the generic
perf features except interrupt overflow and event filtering based on
privilege mode which will be added in future.

It also allows to monitor a handful of firmware counters that can provide
insights into firmware activity during a performance analysis.

Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Add a simple platform driver for RISC-V legacy perf</title>
<updated>2023-01-03T06:26:17+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2021-03-17T23:31:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=42b683064d64a6c52ad909af6aaf1bf01315d634'/>
<id>urn:sha1:42b683064d64a6c52ad909af6aaf1bf01315d634</id>
<content type='text'>
The old RISC-V perf implementation allowed counting of only
cycle/instruction counters using perf. Restore that feature by implementing
a simple platform driver under a separate config to provide backward
compatibility. Any existing software stack will continue to work as it is.
However, it provides an easy way out in future where we can remove the
legacy driver.

Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Add a perf core library for pmu drivers</title>
<updated>2023-01-03T06:26:17+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atish.patra@wdc.com</email>
</author>
<published>2021-03-17T23:18:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=2680fe9e03431db972812ef12ca1b7eb931792ad'/>
<id>urn:sha1:2680fe9e03431db972812ef12ca1b7eb931792ad</id>
<content type='text'>
Implement a perf core library that can support all the essential perf
features in future. It can also accommodate any type of PMU implementation
in future. Currently, both SBI based perf driver and legacy driver
implemented uses the library. Most of the common perf functionalities
are kept in this core library wile PMU specific driver can implement PMU
specific features. For example, the SBI specific functionality will be
implemented in the SBI specific driver.

Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
</feed>
