<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/linux.git/drivers/tty, branch JH7110_VisionFive2_multi_rtos</title>
<subtitle>StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/linux.git/atom?h=JH7110_VisionFive2_multi_rtos</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/linux.git/atom?h=JH7110_VisionFive2_multi_rtos'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/'/>
<updated>2024-03-05T07:18:28+00:00</updated>
<entry>
<title>uart: 8250: add reset operation in runtime PM</title>
<updated>2024-03-05T07:18:28+00:00</updated>
<author>
<name>William Qiu</name>
<email>william.qiu@starfivetech.com</email>
</author>
<published>2023-09-20T09:19:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=9e82665e2ff08285815fc01790b7933bc8f329cc'/>
<id>urn:sha1:9e82665e2ff08285815fc01790b7933bc8f329cc</id>
<content type='text'>
add reset operation in runtime PM

Signed-off-by: William Qiu &lt;william.qiu@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>driver:uart: fix up uart communicate fail</title>
<updated>2024-03-05T07:18:28+00:00</updated>
<author>
<name>shanlong.li</name>
<email>shanlong.li@starfivetech.com</email>
</author>
<published>2023-07-10T10:07:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=77365cc40a9da3131ff563b986b7426abf26c40a'/>
<id>urn:sha1:77365cc40a9da3131ff563b986b7426abf26c40a</id>
<content type='text'>
fix up uart communicate fail

Signed-off-by: shanlong.li &lt;shanlong.li@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>uart: 8250: Add dw auto flow ctrl support</title>
<updated>2024-03-05T07:18:28+00:00</updated>
<author>
<name>Minda Chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-06-25T01:40:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=87a0010eaeeba91929dbf40608beff364ad2de70'/>
<id>urn:sha1:87a0010eaeeba91929dbf40608beff364ad2de70</id>
<content type='text'>
Add designeware 8250 auto flow ctrl support. Enable
it by add auto-flow-control in dts.

Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>serial: amba-pl011: Fix DMA transmission in RS485 mode</title>
<updated>2024-03-01T12:35:02+00:00</updated>
<author>
<name>Lino Sanfilippo</name>
<email>l.sanfilippo@kunbus.com</email>
</author>
<published>2024-02-16T22:47:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=9319ecb8380ffee62a918b08f6146c0e43766463'/>
<id>urn:sha1:9319ecb8380ffee62a918b08f6146c0e43766463</id>
<content type='text'>
commit 3b69e32e151bc4a4e3c785cbdb1f918d5ee337ed upstream.

When DMA is used in RS485 mode make sure that the UARTs tx section is
enabled before the DMA buffers are queued for transmission.

Cc: stable@vger.kernel.org
Fixes: 8d479237727c ("serial: amba-pl011: add RS485 support")
Signed-off-by: Lino Sanfilippo &lt;l.sanfilippo@kunbus.com&gt;
Link: https://lore.kernel.org/r/20240216224709.9928-2-l.sanfilippo@kunbus.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>serial: stm32: do not always set SER_RS485_RX_DURING_TX if RS485 is enabled</title>
<updated>2024-03-01T12:35:02+00:00</updated>
<author>
<name>Lino Sanfilippo</name>
<email>l.sanfilippo@kunbus.com</email>
</author>
<published>2024-02-16T22:47:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=3e3578ca1b877a49a7521e600d51658d6d794267'/>
<id>urn:sha1:3e3578ca1b877a49a7521e600d51658d6d794267</id>
<content type='text'>
commit f418ae73311deb901c0110b08d1bbafc20c1820e upstream.

Before commit 07c30ea5861f ("serial: Do not hold the port lock when setting
rx-during-tx GPIO") the SER_RS485_RX_DURING_TX flag was only set if the
rx-during-tx mode was not controlled by a GPIO. Now the flag is set
unconditionally when RS485 is enabled. This results in an incorrect setting
if the rx-during-tx GPIO is not asserted.

Fix this by setting the flag only if the rx-during-tx mode is not
controlled by a GPIO and thus restore the correct behaviour.

Cc: stable@vger.kernel.org # 6.6+
Fixes: 07c30ea5861f ("serial: Do not hold the port lock when setting rx-during-tx GPIO")
Signed-off-by: Lino Sanfilippo &lt;l.sanfilippo@kunbus.com&gt;
Link: https://lore.kernel.org/r/20240216224709.9928-1-l.sanfilippo@kunbus.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>serial: mxs-auart: fix tx</title>
<updated>2024-02-23T08:25:10+00:00</updated>
<author>
<name>Jiri Slaby (SUSE)</name>
<email>jirislaby@kernel.org</email>
</author>
<published>2024-02-01T10:55:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=5360069666786423f623e2e175ffa62a9aeedeee'/>
<id>urn:sha1:5360069666786423f623e2e175ffa62a9aeedeee</id>
<content type='text'>
commit 7be50f2e8f20fc2299069b28dea59a28e3abe20a upstream.

Emil reports:
  After updating Linux on an i.MX28 board, serial communication over
  AUART broke. When I TX from the board and measure on the TX pin, it
  seems like the HW fifo is not emptied before the transmission is
  stopped.

MXS performs weird things with stop_tx(). The driver makes it
conditional on uart_tx_stopped().

So the driver needs special handling. Pass the brand new UART_TX_NOSTOP
to uart_port_tx_flags() and handle the stop on its own.

Signed-off-by: "Jiri Slaby (SUSE)" &lt;jirislaby@kernel.org&gt;
Reported-by: Emil Kronborg &lt;emil.kronborg@protonmail.com&gt;
Cc: stable &lt;stable@kernel.org&gt;
Fixes: 2d141e683e9a ("tty: serial: use uart_port_tx() helper")
Closes: https://lore.kernel.org/all/miwgbnvy3hjpnricubg76ytpn7xoceehwahupy25bubbduu23s@om2lptpa26xw/
Tested-by: Stefan Wahren &lt;wahrenst@gmx.net&gt;
Tested-by: Emil Kronborg &lt;emil.kronborg@protonmail.com&gt;
Link: https://lore.kernel.org/r/20240201105557.28043-2-jirislaby@kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>serial: max310x: prevent infinite while() loop in port startup</title>
<updated>2024-02-23T08:25:09+00:00</updated>
<author>
<name>Hugo Villeneuve</name>
<email>hvilleneuve@dimonoff.com</email>
</author>
<published>2024-01-16T21:30:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=24ea2c4d48645d3ddf1d40f5a98c36a0052d07e3'/>
<id>urn:sha1:24ea2c4d48645d3ddf1d40f5a98c36a0052d07e3</id>
<content type='text'>
commit b35f8dbbce818b02c730dc85133dc7754266e084 upstream.

If there is a problem after resetting a port, the do/while() loop that
checks the default value of DIVLSB register may run forever and spam the
I2C bus.

Add a delay before each read of DIVLSB, and a maximum number of tries to
prevent that situation from happening.

Also fail probe if port reset is unsuccessful.

Fixes: 10d8b34a4217 ("serial: max310x: Driver rework")
Cc: stable@vger.kernel.org
Signed-off-by: Hugo Villeneuve &lt;hvilleneuve@dimonoff.com&gt;
Link: https://lore.kernel.org/r/20240116213001.3691629-5-hugo@hugovil.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>serial: max310x: fail probe if clock crystal is unstable</title>
<updated>2024-02-23T08:25:09+00:00</updated>
<author>
<name>Hugo Villeneuve</name>
<email>hvilleneuve@dimonoff.com</email>
</author>
<published>2024-01-16T21:30:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=89992713f3647ee60122360d20b2d00872fae84f'/>
<id>urn:sha1:89992713f3647ee60122360d20b2d00872fae84f</id>
<content type='text'>
commit 8afa6c6decea37e7cb473d2c60473f37f46cea35 upstream.

A stable clock is really required in order to use this UART, so log an
error message and bail out if the chip reports that the clock is not
stable.

Fixes: 4cf9a888fd3c ("serial: max310x: Check the clock readiness")
Cc: stable@vger.kernel.org
Suggested-by: Jan Kundrát &lt;jan.kundrat@cesnet.cz&gt;
Link: https://www.spinics.net/lists/linux-serial/msg35773.html
Signed-off-by: Hugo Villeneuve &lt;hvilleneuve@dimonoff.com&gt;
Link: https://lore.kernel.org/r/20240116213001.3691629-4-hugo@hugovil.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>serial: max310x: improve crystal stable clock detection</title>
<updated>2024-02-23T08:25:09+00:00</updated>
<author>
<name>Hugo Villeneuve</name>
<email>hvilleneuve@dimonoff.com</email>
</author>
<published>2024-01-16T21:29:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=2655f0892c046c32438d9df257c3a067ecdc6aae'/>
<id>urn:sha1:2655f0892c046c32438d9df257c3a067ecdc6aae</id>
<content type='text'>
commit 93cd256ab224c2519e7c4e5f58bb4f1ac2bf0965 upstream.

Some people are seeing a warning similar to this when using a crystal:

    max310x 11-006c: clock is not stable yet

The datasheet doesn't mention the maximum time to wait for the clock to be
stable when using a crystal, and it seems that the 10ms delay in the driver
is not always sufficient.

Jan Kundrát reported that it took three tries (each separated by 10ms) to
get a stable clock.

Modify behavior to check stable clock ready bit multiple times (20), and
waiting 10ms between each try.

Note: the first draft of the driver originally used a 50ms delay, without
checking the clock stable bit.
Then a loop with 1000 retries was implemented, each time reading the clock
stable bit.

Fixes: 4cf9a888fd3c ("serial: max310x: Check the clock readiness")
Cc: stable@vger.kernel.org
Suggested-by: Jan Kundrát &lt;jan.kundrat@cesnet.cz&gt;
Link: https://www.spinics.net/lists/linux-serial/msg35773.html
Link: https://lore.kernel.org/all/20240110174015.6f20195fde08e5c9e64e5675@hugovil.com/raw
Link: https://github.com/boundarydevices/linux/commit/e5dfe3e4a751392515d78051973190301a37ca9a
Signed-off-by: Hugo Villeneuve &lt;hvilleneuve@dimonoff.com&gt;
Link: https://lore.kernel.org/r/20240116213001.3691629-3-hugo@hugovil.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>serial: max310x: set default value when reading clock ready bit</title>
<updated>2024-02-23T08:25:09+00:00</updated>
<author>
<name>Hugo Villeneuve</name>
<email>hvilleneuve@dimonoff.com</email>
</author>
<published>2024-01-16T21:29:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/linux.git/commit/?id=8c6df38c7033331528c138d888ec77770ac23504'/>
<id>urn:sha1:8c6df38c7033331528c138d888ec77770ac23504</id>
<content type='text'>
commit 0419373333c2f2024966d36261fd82a453281e80 upstream.

If regmap_read() returns a non-zero value, the 'val' variable can be left
uninitialized.

Clear it before calling regmap_read() to make sure we properly detect
the clock ready bit.

Fixes: 4cf9a888fd3c ("serial: max310x: Check the clock readiness")
Cc: stable@vger.kernel.org
Signed-off-by: Hugo Villeneuve &lt;hvilleneuve@dimonoff.com&gt;
Link: https://lore.kernel.org/r/20240116213001.3691629-2-hugo@hugovil.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
</feed>
